The recent progress in nanosheet transistors has established two-dimensional (2D) semiconductors as viable candidates for future ultra-scaled electronic devices. Next to reducing contact resistance, identifying good gate dielectrics is a fundamental challenge, as the dielectric/channel interface dramatically impacts virtually all performance parameters. While several promising gate dielectrics have recently been reported, the evaluation of their quality and suitability is often fragmentary and focused on selected important performance metrics of the gate stack, such as the capacitive gate control, leakage currents, reliability, and ease of fabrication and integration. However, identifying a suitable gate stack is a complex problem that has not yet been approached systematically. In this perspective, we aim to formulate general criteria for good gate dielectrics.
@article{arxiv.2509.20014,
title = {How to Identify Suitable Gate Dielectrics for Transistors based on Two-Dimensional Semiconductors},
author = {Theresia Knobloch and Quentin Smets and Anton E. O. Persson and Pedram Khakbaz and Christoph Wilhelmer and Dennis Lin and Zherui Han and Yunyan Chung and Kevin P. OBrien and Chelsey Dorow and Cormac OCoileain and Mario Lanza and Dominic Waldhoer and Alexander Karl and Kailang Liu and Tianyou Zhai and Hailin Peng and Congwei Tan and Xiao Renshaw Wang and Georg S. Duesberg and John Robertson and Uygar Avci and Iuliana Radu and Eric Pop and Cesar J. Lockhart de la Rosa and Tibor Grasser},
journal= {arXiv preprint arXiv:2509.20014},
year = {2025}
}