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We report electronic transport on n-type silicon Single Electron Transistors (SETs) fabricated in Complementary Metal Oxide Semiconductor (CMOS) technology. The n-MOSSETs are built within a pre-industrial Fully Depleted Silicon On Insulator…
In the upgrade of ATLAS experiment, the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector…
The development of CMOS pixel sensors with column parallel read-out and integrated zero-suppression has resulted in a full size, nearly 1 Megapixel, prototype with ~100 \mu s read-out time. Its performances are quite close to the ILD vertex…
In contemporary general-purpose graphics processing units (GPGPUs), the continued increase in raw arithmetic throughput is constrained by the capabilities of the register file (single-cycle) and last-level cache (high bandwidth), which…
This paper presents a comprehensive analysis of the RISC-V instruction set architecture, focusing on its modular design, implementation challenges, and performance characteristics. We examine the RV32I base instruction set with extensions…
The experiment of the future electron-positron colliders has unprecedented requirements on the vertex resolution, such as around 3micron single point resolution for the inner most detector layer, with fast readout, and very low…
The ATLAS detector at LHC will require a Trigger system to efficiently select events down to a manageable event storage rate of about 400 Hz. By 2015 the LHC instantaneous luminosity will be increased up to 3 x 10^34 cm-2s-1, this…
In this paper, we investigated a gate driver using a GaN HEMT push-pull configuration for the high-frequency hard switching of a SiC power MOSFET. Low on-resistance and low input capacitance of GaN HEMTs are suitable for a high-frequency…
CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a…
For experiments at the European X-Ray Free-Electron Laser (XFEL) the Adaptive Gain Integrating Pixel Detector (AGIPD) is under development. The particular requirements for the detector are a high dynamic range of 0, 1 - to more than 10E4…
Cornell's electron/positron storage ring (CESR) was modified over a series of accelerator shutdowns beginning in May 2008, which substantially improves its capability for research and development for particle accelerators. CESR's energy…
We present an automated protocol for tuning single-electron transistors (SETs) and single-hole transistors (SHTs) to operate as high-sensitivity DC charge sensors. The protocol initializes a previously unmeasured device after cooldown,…
We demonstrate an optical data wavelength converter based on an electrically driven photonic molecule structure comprising two coupled active silicon microring resonators. The converter, supplied by a continuous-wave (CW) microwave drive…
Cornell's electron/positron storage ring (CESR) was modified over a series of accelerator shutdowns beginning in May 2008, which substantially improves its capability for research and development for particle accelerators. CESR's energy…
Quantum computing (QC) requires cryogenic electronic circuits as control and readout sub-systems of quantum chips to meet the qubit scale-up challenges.At this temperature,MOSFETs transistors exhibition many changes such as higher threshold…
We demonstrate a gate dielectric engineering approach leveraging an ultrathin, atomic layer deposited (ALD) silicon oxide interfacial layer (SiL) between the amorphous oxide semiconductor (AOS) channel and the high-k gate dielectric. SiL…
High-Voltage Monolithic Active Pixel Sensors (HV-MAPS) based on the 180 nm HV-CMOS process have been proposed to realize thin, fast and highly integrated pixel sensors. The MuPix7 prototype, fabricated in the commercial AMS H18 process,…
Modern Systems on Chip (SoC), almost as a rule, require accelerators for achieving energy efficiency and high performance for specific tasks that are not necessarily well suited for execution in standard processing units. Considering the…
We have developed a quantum annealing processor, based on an array of tunably coupled rf-SQUID flux qubits, fabricated in a superconducting integrated circuit process [1]. Implementing this type of processor at a scale of 512 qubits and…
The 3rd Generation Partnership Project released the cellular vehicular-to-everything (C-V2X) specifications as part of the LTE framework in Release 14. C-V2X is the alternative to dedicated short range communications and both are…