Related papers: Active inductor shunt peaking in high-speed VCSEL …

We have been developing event driven X-ray Silicon-On-Insulator (SOI) pixel sensors, called "XRPIX", for the next generation of X-ray astronomy satellites. XRPIX is a monolithic active pixel sensor, fabricated using the SOI CMOS technology,…

Monolithic active pixel sensors produced in High Voltage CMOS (HV-CMOS) technology are being considered for High Energy Physics applications due to the ease of production and the reduced costs. Such technology is especially appealing when…

As hyperscale and co-located data centers scale, the electric grid sees an increase in large, voltage-sensitive IT loads with these data center plant size ranging between 500 MW to 2 GW. A sudden loss of these loads as they switch to onsite…

Silicon pixel sensors manufactured using commercial CMOS processes are promising instruments for high-energy particle physics experiments due to their high yield and proven radiation hardness. As one of the essential factors for the…

This work focuses on an efficient Agile design methodology for domain-specific accelerators. We employ feature-by-feature enhancement of a vertical development stack and apply it to the TVM/VTA inference accelerator. We have enhanced the…

Spiking neural networks (SNNs), which are inspired by the human brain, have recently gained popularity due to their relatively simple and low-power hardware for transmitting binary spikes and highly sparse activation maps. However, because…

A magnetic bunch compressor has been designed and is being commissioned for the APS linac to provide higher peak current for the LEUTL FEL. Of primary concern is control of emittance growth due to coherent synchrotron radiation (CSR). In…

An upgrade of the ATLAS experiment for the High Luminosity phase of LHC is planned for 2024 and foresees the replacement of the present Inner Detector (ID) with a new Inner Tracker (ITk) completely made of silicon devices. Depleted active…

The vertical-cavity surface-emitting lasers (VCSELs) have emerged as a vital approach for realizing energy efficient, high speed optical interconnects in the data center and supercomputers. As of today, VCSEL is the most suitable for mass…

A single channel 1.5GS/s 8-bit pipelined-SAR ADC utilizes a novel output level shifting (OLS) settling technique to reduce the power and enable low-voltage operation of the dynamic residue amplifier. The ADC consists of a 4-bit first stage…

It is shown that the noise-limited charge sensitivity of a single-electron transistor using superconductors (of either $SISIS$ or $NISIN$ type) operating near the threshold of quasiparticle tunneling, can be considerably higher than that of…

Quantum processing units will be modules of larger information processing systems containing also digital and analog electronics modules. Silicon-based quantum computing offers the enticing opportunity to manufacture all the modules using…

We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by TSMC has been optimized for 50 um thick AC-LGAD. The evaluation of the analog front end…

Why do security cameras, sensors, and siri use cloud servers instead of on-board computation? The lack of very-low-power, high-performance chips greatly limits the ability to field untethered edge devices. We present the NV-1, a new…

Cornell's electron/positron storage ring (CESR) was modified over a series of accelerator shutdowns beginning in May 2008, which substantially improves its capability for research and development for particle accelerators. CESR's energy…

In this paper we present a novel, quadruple well process developed in a modern 0.18mu CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening…

The upcoming ATLAS Phase II upgrade mandates replacing the tracking system with the all-silicon Inner Tracker (ITK), featuring a pixel detector as its core element. The monitoring data of the new system will be aggregated from an…

We present a DevIce-to-System Performance EvaLuation (DISPEL) workflow that integrates transistor and interconnect modeling, parasitic extraction, standard cell library characterization, logic synthesis, cell placement and routing, and…

Brain-inspired, neuromorphic devices implemented in integrated photonic hardware have attracted significant interest recently as part of efforts towards novel non-von Neumann computing paradigms that make use of the low loss, high-speed and…

Use of 2G HTS coated conductors in several power applications has become popular in recent years. Their large current density under high magnetic fields makes them suitable candidates for high power capacity applications such as stacks,…