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In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area…

There are increasing number of works addressing the design challenges of fast, scalable solutions for the growing number of new type of applications. Recently, many of the solutions aimed at improving processing element capabilities to…

Hardware Architecture · Computer Science 2019-12-16 Somnath Mazumdar , Alberto Scionti

We present XgenSilicon ML Compiler, a fully automated end-to-end compilation framework that transforms high-level machine learning models into optimized RISC-V assembly code for custom ASIC accelerators. By unifying the system's cost model…

Hardware Architecture · Computer Science 2025-12-02 Ravindra Ganti , Steve Xu

Velocity-controlled spatio-temporal (ST) laser drivers offer a route to tailoring laser-plasma interactions by allowing the velocity of the intensity peak to be controlled independently of the envelope group velocity. In this work, we…

Plasma Physics · Physics 2026-04-28 Chiara Badiali , Rafael Almeida , Thales Silva , Jorge Vieira

With the increase of the speed of computers, timing and power requirements are becoming crucial for memory devices. The main objective of the paper is to modify 180nm CMOS sense amplifier design by using memristive devices and improve the…

Emerging Technologies · Computer Science 2019-08-28 Yerlan Amanzholov , Olga Krestinskaya

This paper presents SleepViT, a custom accelerator ASIC for real-time, low-power sleep stage classification in wearable devices. At the core of SleepViT is a lightweight vision transformer model specifically optimized for…

Signal Processing · Electrical Eng. & Systems 2025-09-08 Tristan Robitaille , Xilin Liu

We describe the details of a silicon-tungsten prototype electromagnetic calorimeter module and associated readout electronics. Detector performance for this prototype has been measured in test beam experiments at the CERN PS and SPS…

For the Inner Tracking System 3 (ITS3) upgrade, the ALICE experiment at CERN requires monolithic active pixel sensors of dimensions up to 97~mm$\,\times\,$266~mm, occupying a large fraction of a 300 mm wafer. To manufacture such a…

Recently, intermittent computing (IC) has received tremendous attention due to its high potential in perpetual sensing for Internet-of-Things (IoT). By harvesting ambient energy, battery-free devices can perform sensing intermittently…

Networking and Internet Architecture · Computer Science 2023-08-17 Gaosheng Liu , Lin Wang

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active…

Instrumentation and Detectors · Physics 2017-10-06 I. Kremastiotis , R. Ballabriga , M. Campbell , D. Dannheim , A. Fiergolski , D. Hynds , S. Kulis , I. Peric

Compute-in-memory (CIM) accelerators for spiking neural networks (SNNs) are promising solutions to enable $\mu$s-level inference latency and ultra-low energy in edge vision applications. Yet, their current lack of flexibility at both the…

Hardware Architecture · Computer Science 2024-10-31 Nicolas Chauvaux , Adrian Kneip , Christoph Posch , Kofi Makinwa , Charlotte Frenkel

As semiconductor power density is no longer constant with the technology process scaling down, modern CPUs are integrating capable data accelerators on chip, aiming to improve performance and efficiency for a wide range of applications and…

Hardware Architecture · Computer Science 2024-01-31 Reese Kuper , Ipoom Jeong , Yifan Yuan , Jiayu Hu , Ren Wang , Narayan Ranganathan , Nam Sung Kim

As the scaling of conventional CMOS-based technologies slows down, there is growing interest in alternative technologies that can improve performance or energy-efficiency. Superconducting circuits based on Josephson Junction (JJ) is an…

Hardware Architecture · Computer Science 2019-02-15 Swamit S. Tannu , Poulami Das , Michael L. Lewis , Robert Krick , Douglas M. Carmean , Moinuddin K. Qureshi

We demonstrate and experimentally validate an end-to-end hybrid CMOS-memristor auditory encoder that realises adaptive-threshold, asynchronous delta-modulation (ADM)-based spike encoding by exploiting the inherent volatility of HfTiOx…

Audio and Speech Processing · Electrical Eng. & Systems 2025-12-08 Dongxu Guo , Deepika Yadav , Patrick Foster , Spyros Stathopoulos , Mingyi Chen , Themis Prodromakis , Shiwei Wang

Graphene/silicon heterostructures have attracted tremendous interest as a new platform for diverse electronic and photonic devices such as barristors, solar cells, optical modulators, and chemical sensors. The studies to date largely focus…

Materials Science · Physics 2015-12-29 Yuan Liu , Jiming Sheng , Hao Wu , Qiyuan He , Hung-Chieh Cheng , Muhammad Imran Shakir , Yu Huang , Xiangfeng Duan

AMD Xilinx's new Versal Adaptive Compute Acceleration Platform (ACAP) is an FPGA architecture combining reconfigurable fabric with other on-chip hardened compute resources. AI engines are one of these and, by operating in a highly…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-01-31 Nick Brown

We present the electro-thermal characterization of transition-edge sensor (TES) detectors suspended on Si membranes fabricated using a silicon-on-insulator (SOI) wafer. The use of an all-silicon fabrication platform, in contrast to the more…

Superinductors are circuit elements characterised by an intrinsic impedance in excess of the superconducting resistance quantum ($R_\text{Q}\approx6.45~$k$\Omega$), with applications from metrology and sensing to quantum computing. However,…

Thin (6-7 quintuple layer) topological insulator Bi2Se3 quantum dot devices are demonstrated using ultrathin (2~4 quintuple layer) Bi2Se3 regions to realize semiconducting barriers which may be tuned from Ohmic to tunneling conduction via…

Mesoscale and Nanoscale Physics · Physics 2012-01-19 Sungjae Cho , Dohun Kim , Paul Syers , Nicholas P. Butch , Johnpierre Paglione , Michael S. Fuhrer

Our goal in this paper is to understand how to maximize energy efficiency when designing standard-ISA processor cores for subthreshold operation. We hence develop a custom subthreshold library and use it to synthesize the open-source RISC-V…

Hardware Architecture · Computer Science 2025-02-11 Asbjørn Djupdal , Magnus Själander , Magnus Jahre , Snorre Aunet , Trond Ytterdal
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