Related papers: Balanced ternary addition using a gated silicon na…

A simple and highly reproducible single electron transistor (SET) has been fabricated using gated silicon nanowires. The structure is a metal-oxide-semiconductor field-effect transistor made on silicon-on-insulator thin films. The channel…

Single Electron Transistors (SETs) are nanoscale electrometers of unprecedented sensitivity, and as such have been proposed as read-out devices in a number of quantum computer architectures. We show that the functionality of a standard SET…

A dual mode device behaving either as a field-effect transistor or a single electron transistor (SET) has been fabricated using silicon-on-insulator metal oxide semiconductor technology. Depending on the back gate polarisation, an electron…

We propose and numerically analyze novel reconfigurable logic gates using "single-electron spin transistors" (SESTs), which are single-electron transistors (SETs) with ferromagnetic electrodes and islands. The output characteristics of a…

The design of balanced ternary digital logic circuits based on memristors and conventional CMOS devices is proposed. First, balanced ternary minimum gate TMIN, maximum gate TMAX and ternary inverters are systematically designed and verified…

This paper presents a ternary half adder and a 1-trit multiplier using carbon nanotube transistors. The proposed circuits are designed using pass transistor logic and dynamic logic. Ternary logic uses less connections than binary logic, and…

Traditional silicon binary circuits continue to face challenges such as high leakage power dissipation and large area of interconnections. Multiple-Valued Logic (MVL) and nano devices are two feasible solutions to overcome these problems.…

We have suspended an Al based single-electron transistor whose island can resonate freely between the source and drain leads forming the clamps. In addition to the regular side gate, a bottom gate with a larger capacitance to the SET island…

We present a novel reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consist of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the…

An important consideration in miniaturizing transistors is maximizing the coupling between the gate and the semiconductor channel. A nanowire with a coaxial metal gate provides optimal gate-channel coupling, but has only been realized for…

Single dopants in semiconductor nanostructures have been studied in great details recently as they are good candidates for quantum bits, provided they are coupled to a detector. Here we report coupling of a single As donor atom to a…

We introduce a silicon metal-oxide-semiconductor quantum dot architecture based on a single polysilicon gate stack. The elementary structure consists of two enhancement gates separated spatially by a gap, one gate forming a reservoir and…

We report electronic transport on silicon double and triple dots created with the optimized number of two gates. Using silicon nitride spacers two dots in series are created below two top gates overlapping a silicon nanowire. Coupling…

We consider a single-electron transistor (SET) whose central island is a nanomechanical oscillator. The gate capacitance of the SET depends on the mechanical displacement, thus, the vibrations of the island vibrations may strongly influence…

The advanced nanoscale integration available in silicon complementary metal-oxide-semiconductor (CMOS) technology provides a key motivation for its use in spin-based quantum computing applications. Initial demonstrations of quantum dot…

We present a systematic study of various ways (top gates, local doping, substrate bias) to fabricate and tune multi-dot structures in silicon nanowire multigate MOSFETs (metal-oxide-semiconductor field-effect transistors). The carrier…

Ternary logic is expected to increase the area efficiency of VLSI due to its expressiveness compared to the traditional binary logic. This paper proposes a new symmetric ternary logic and a systematic logic composition methodology that…

As transistor dimensions continue to shrink, binary devices are rapidly approaching their fundamental limits in power density. In response, multi-valued systems have attracted significant attention due to their enhanced information density.…

The design of systems implementing low precision neural networks with emerging memories such as resistive random access memory (RRAM) is a significant lead for reducing the energy consumption of artificial intelligence. To achieve maximum…

A demonstration that e=2.718 rounded to 3 is the best radix for computation is disproved. The MOSFET-like CNTFET technology is used to compare inverters, Nand, adders, multipliers, D Flip-Flops and SRAM cells. The transistor count ratio…