Related papers: Balanced ternary addition using a gated silicon na…
This thesis proposes novel ternary circuits aiming to reduce energy to preserve battery consumption. The proposed designs include eight ternary logic gates, three ternary combinational circuits, and six Ternary Arithmetic Logic Units. This…
This paper investigates the potentials of using a hybrid memristor CMOS technology, called MeMOS, for the realisation of ternary adders. Ternary adders exploit the qualitative advantage of multi-value storage capability of memristors…
We report on experiments performed on a cantilever-based tri-port nano-electro-mechanical (NEMS) device. Two ports are used for actuation and detection through the magnetomotive scheme, while the third port is a capacitively coupled gate…
Quantum mechanical effects induced by the miniaturization of complementary metal-oxide-semiconductor (CMOS) technology hamper the performance and scalability prospects of field-effect transistors. However, those quantum effects, such as…
A nanoscale device consisting of a metal nanowire, a dielectric, and a gate is proposed. A combination of quantum and thermal stochastic effects enable the device to have multiple functionalities, serving alternately as a transistor, a…
We report room-temperature Coulomb blockade in a single layer graphene three-terminal single-electron transistor (SET) fabricated using feedback-controlled electroburning. The small separation between the side gate electrode and the…
We compare charge transitions on a deterministic single P donor in silicon using radio frequency reflectometry measurements with a tunnel coupled reservoir and DC charge sensing using a capacitively coupled single electron transistor (SET).…
We present a gate-voltage tunable transmon qubit (gatemon) based on planar InAs nanowires that are selectively grown on a high resistivity silicon substrate using III-V buffer layers. We show that low loss superconducting resonators with an…
Reducing delay, power consumption, and chip area of a logic circuit are the main targets of a designer. Most of the times, the designer sacrifices power consumption and chip area to improve delay for a given technology node. To overcome…
We describe critical processing issues in our development of single atom devices for solid-state quantum information processing. Integration of single 31P atoms with control gates and single electron transistor (SET) readout structures is…
Gate capacitances of back-gated nanowire field-effect transistors (NW-FETs) are calculated by means of finite element methods and the results are compared with analytical results of the ``metallic cylinder on an infinite metal plate…
The density of states of proximitized normal nanowires interrupting superconducting rings can be tuned by the magnetic flux piercing the loop. Using these as the contacts of a single-electron transistor allows to control the energetic…
A single-electron inverter was fabricated that switches from a high output to a low output when a fraction of an electron is added to the input. For the proper operation of the inverter, the two single-electron transistors that make up the…
In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272$\mu$W in 0.35$\mu$m technology with supply voltage of 3.3V. Minimum level for high output of 2.05V and maximum level for…
We report the operation of a field-effect transistor based on a single InAs nanowire gated by an ionic liquid. Liquid gating yields very efficient carrier modulation with a transconductance value thirty time larger than standard back gating…
We report charge sensing measurements on a silicon quantum dot (QD) with a nearby silicon single electron transistor (SET) acting as an electrometer. The devices are electrostatically formed in bulk silicon using surface gates. We show that…
The electronic conduction of a novel, three-terminal molecular architecture, analogous to a heterojunction bipolar transistor is studied. In this architecture, two diode arms consisting of donor-acceptor molecular wires fuse through a ring,…
In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We…
In this study, we construct the quantum reversible counterparts of the logical AND, OR, XOR, NOR, and NAND gates. We utilize a quantum Fourier transform (QFT)-based adder circuit that replicates the functionality of a digital half-adder,…
We have analyzed numerically the response and noise-limited charge sensitivity of a radio-frequency single-electron transistor (RF-SET) in a non-superconducting state using the orthodox theory. In particular, we have studied the performance…