Related papers: Performance evaluation of FD-SOI Mosfets for diffe…

In this letter we discuss how the short channel behavior in sub 100 nm channel range can be improved by inducing a step surface potential profile at the back gate of an asymmetrical double gate (DG) Silicon-On-Insulator (SOI)…

In this paper we have developed a two dimensional (2D) analytical model for surface potential and drain current for a long channel Dual Material Gate (DMG) Silicon-on-Insulator (SOI) Tunneling Field Effect Transistor (TFET). This model…

The doped silicon regions (tubs) in PWFDSOI MOSFET cause significant reduction in OFF current by reducing the number of carriers contributing to the OFF current. The emphasis of the simulation and device physics study on PWFDSOI MOSFET…

Multiple-gate SOI MOSFETs with gate length equal to 25 nm are compared using device Monte Carlo simulation. In such architectures, the short channel effects may be controlled with much less stringent body and oxide thickness requirements…

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed…

Silicon carbide (SiC) metal-oxide-semiconductor field-effect-transistors (MOSFETs) enable high-voltage and high-temperature power conversion. Compared to Si devices, they suffer from pronounced gate leakage due to the reduced electron…

The paper presents simulation study of thin ferroelectrics (Si doped HfO2, PZT) PGP FDSOI NCFETs at circuit level for high performance, low VDD low-power digital circuits. The baseline PGP FDSOI MOSFET has 20 nm metal gate length with…

Traditional transistors based on complementary metal-oxide-semiconductor (CMOS) and metal-oxide-semiconductor field-effect transistors (MOSFETs) are facing significant limitations as device scaling reaches the limits of Moore's Law. These…

Capacitance-Voltage (C-V) & Ballistic Current- Voltage (I-V) characteristics of Double Gate (DG) Silicon-on- Insulator (SOI) Flexible FETs having sub 35nm dimensions are obtained by self-consistent method using coupled Schrodinger- Poisson…

In this paper, we present the unique features exhibited by modified asymmetrical Double Gate (DG) silicon on insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the…

Two-dimensional (2D) layered materials-based field-effect transistors (FETs) are promising for ultimate scaled electron device applications because of the improved electrostatics to atomically thin body thickness. However, compared with the…

A novel planar device having doped silicon regions (tubs) under the source and drain of an FDSOI MOSFET is reported at 20 nm gate length. The doped silicon regions result in formation of potential wells (PW) in the source and drain regions…

In this work, we propose a new Stepped Oxide Hetero-Material Trench (SOHMT) power MOSFET with three sections in the trench gate (an N+ poly gate sandwiched between two P+ poly gates) and having different gate oxide thicknesses (increasing…

Gate tunable p-type multilayer tin mono-sulfide (SnS) field-effect transistor (FET) devices with SnS thickness between 50 and 100 nm were fabricated and studied to understand their performances. The devices showed anisotropic inplane…

Excellent gate electrostatics in field effect transistors (FETs) based on two-dimensional transition metal dichalcogenide (2D TMD) channels can dramatically decrease static power dissipation. Energy efficient FETs operate in enhancement…

In this work, we propose an explicit analytical equation to show the variation of top gate threshold voltage with respect to the JFET bottom gate voltage for a Flexible Threshold Voltage Field Effect Transistor (Flexible-FET) by solving 2-D…

The performance and scalability of two-dimensional (2D) field-effect transistors (FETs) are strongly influenced by geometry-defined electrostatics. In most 2D FET studies, the gate overlaps with the source and drain electrodes, allowing the…

In this paper, we have presented the impact of the gate leakage through thin gate dielectrics (SiO2 and high-\k{appa} gate dielectric) on the subthreshold characteristics of the tunnel field effect transistors (TFET) for a low operating…

Recently, short channel effects (SCE) and power consumption dissipation problems pose big challenges which need imperative actions to be taken to deal with for field effect transistor to further scale down as semiconductor technology enters…

We proposed a new high resolution single photon infrared spectrometer for search for radiative decay of cosmic neutrino background(C$\nu$B). The superconducting-tunnel-junctions(STJs) are used as a single photoncounting device. Each STJ…