Floating Point HUB Adder for RISC-V Sargantana Processor

Gerardo Bandera; Javier Salamero; Miquel Moreto; Julio Villalba

Floating Point HUB Adder for RISC-V Sargantana Processor

Hardware Architecture 2024-01-19 v1

Authors: Gerardo Bandera , Javier Salamero , Miquel Moreto , Julio Villalba

Abstract

HUB format is an emerging technique to improve the hardware and time requirement when round to nearest is needed. On the other hand, RISC-V is an open-source ISA that many companies currently use in their designs. This paper presents a tailored floating point HUB adder implemented in the Sargantana RISC-V processor.

Cite

@article{arxiv.2401.09464,
  title  = {Floating Point HUB Adder for RISC-V Sargantana Processor},
  author = {Gerardo Bandera and Javier Salamero and Miquel Moreto and Julio Villalba},
  journal= {arXiv preprint arXiv:2401.09464},
  year   = {2024}
}

Comments

RISC-V Summit Europe, Barcelona, 5-9th June 2023

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