We propose and demonstrate a relaxed-SiGe/strained-Si (SiGe/s-Si) enhancement-mode gate stack for quantum dots. The enhancement-mode SiGe/s-Si structure is pursued because it spaces the quantum dot away from charge and spin defect rich dielectric interfaces and minimizes background dopants. A mobility of 1.6\times10^5 cm^2/Vs at 5.8\times10^{11}/cm^2 is measured in Hall bars that witness the same device process flow as the quantum dot. Periodic Coulomb blockade (CB) is measured in a double-top-gated lateral quantum dot nanostructure. The CB terminates with open diamonds up to \pm 10 mV of DC voltage across the device. The devices were fabricated within a 150 mm Si foundry setting that uses implanted ohmics and chemical-vapor-deposited dielectrics, in contrast to previously demonstrated enhancement-mode SiGe/s-Si structures made with AuSb alloyed ohmics and atomic-layer-deposited dielectric. A modified implant, polysilicon formation and annealing conditions were utilized to minimize the thermal budget so that the buried s-Si layer would not be washed out by Ge/Si interdiffusion.
@article{arxiv.1106.0337,
title = {Enhancement-mode buried strained silicon channel quantum dot with tunable lateral geometry},
author = {T. M. Lu and N. C. Bishop and T. Pluym and J. Means and P. G. Kotula and J. Cederberg and L. A. Tracy and J. Dominguez and M. P. Lilly and M. S. Carroll},
journal= {arXiv preprint arXiv:1106.0337},
year = {2011}
}