相关论文: FPGA Co-processor for the ALICE High Level Trigger

A deep-learning inference accelerator is synthesized from a C-language software program parallelized with Pthreads. The software implementation uses the well-known producer/consumer model with parallel threads interconnected by FIFO queues.…

We develop and study FPGA implementations of algorithms for charged particle tracking based on graph neural networks. The two complementary FPGA designs are based on OpenCL, a framework for writing programs that execute across heterogeneous…

The high $P_T$ trigger capabilities of the ALICE inner tracking system (ITS) as a standalone detector have been investigated. Since the high $P_T$ charged particles mostly lead to the linear trajectories within this ITS sector, it is…

C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for field-programmable gate array (FPGA) accelerators in many application domains in recent years, thanks to its competitive quality of results (QoR) and short…

ALICE (A Large Ion Collider Experiment) experiment at CERN LHC is designed to study the properties of the Quark-Gluon Plasma (QGP) in heavy-ion collisions. In 2019-2020 the upgrade of CERN LHC will increase the luminosity and the collision…

ALICE is the dedicated heavy-ion experiment at the CERN Large Hadron Collider (LHC). Its main tracking and particle-identification detector is a large volume Time Projection Chamber (TPC). The TPC has been designed to perform well in the…

Machine Learning (ML) has been widely adopted in design exploration using high level synthesis (HLS) to give a better and faster performance, and resource and power estimation at very early stages for FPGA-based design. To perform…

Field Programmable Gate Arrays (FPGAs) have the potential to accelerate specific HPC codes. However even with the advent of High Level Synthesis (HLS), which enables FPGA programmers to write code in C or C++, programming such devices still…

Dynamic programming (DP) based algorithms are essential yet compute-intensive parts of numerous bioinformatics pipelines, which typically involve populating a 2-D scoring matrix based on a recursive formula, optionally followed by a…

The ATLAS Fast TracKer (FTK) was designed to provide full tracking for the ATLAS high-level trigger by using pattern recognition based on Associative Memory (AM) chips and fitting in high-speed field programmable gate arrays. The tracks…

The Large Hadron Collider (LHC) at the European Organization for Nuclear Research (CERN) is the world's largest and most powerful particle accelerator colliding beams of protons and lead ions at energies up to 7 ZTeV, Z is the atomic…

The ATLAS Trigger system is a key component of the ATLAS experiment at the CERN Large Hadron Collider (LHC), designed to reduce the event rate from the 40 MHz proton-proton bunch crossing frequency to an output suitable for offline storage…

Field-Programmable Gate Arrays (FPGAs) are widely used in the central signal processing design of the Square Kilometre Array (SKA) as acceleration hardware. The frequency domain acceleration search (FDAS) module is an important part of the…

Recently, large language models (LLMs) have achieved huge success in the natural language processing (NLP) field, driving a growing demand to extend their deployment from the cloud to edge devices. However, deploying LLMs on…

To fully exploit the physics potential of current and future high energy particle colliders, machine learning (ML) can be implemented in detector electronics for intelligent data processing and acquisition. The implementation of ML in…

The implementation of convolutional neural networks in programmable logic, for applications in fast online event selection at hadron colliders is studied. In particular, an approach based on full event images for classification is studied,…

The ALICE experiment has undergone a major upgrade for LHC Run 3 and will collect data at an interaction rate 50 times larger than before. The new computing scheme for Run 3 replaces the traditionally separate online and offline frameworks…

FPGA technology can offer significantly hi\-gher performance at much lower power consumption than is available from CPUs and GPUs in many computational problems. Unfortunately, programming for FPGA (using ha\-rdware description languages,…

This proceeding provides an expanded overview of the Fast Interaction Trigger (FIT) system performance, focusing on new developments such as the prospective integration of the ALICE Low-Level Front-End Device (ALFRED) into the Detector…

FPGA-based accelerators are becoming more popular for deep neural network due to the ability to scale performance with increasing degree of specialization with dataflow architectures or custom data types. To reduce the barrier for software…