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相关论文: DREAMPlaceFPGA-MP: An Open-Source GPU-Accelerated …

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Placement is crucial in the physical design, as it greatly affects power, performance, and area metrics. Recent advancements in analytical methods, such as DREAMPlace, have demonstrated impressive performance in global placement. However,…

机器学习 · 计算机科学 2024-02-29 Ke Xue , Xi Lin , Yunqi Shi , Shixiong Kai , Siyuan Xu , Chao Qian

This paper proposes OpenPARF, an open-source placement and routing framework for large-scale FPGA designs. OpenPARF is implemented with the deep learning toolkit PyTorch and supports massive parallelization on GPU. The framework proposes a…

硬件体系结构 · 计算机科学 2023-06-30 Jing Mai , Jiarui Wang , Zhixiong Di , Guojie Luo , Yun Liang , Yibo Lin

On modern field-programmable gate arrays (FPGAs), certain critical path portions of the designs might be prearranged into many multi-cell macros during synthesis. These movable macros with constraints of shape and resources lead to…

硬件体系结构 · 计算机科学 2023-05-04 Tingyuan Liang , Gengjie Chen , Jieru Zhao , Sharad Sinha , Wei Zhang

Recent trends in business and technology (e.g., machine learning, social network analysis) benefit from storing and processing growing amounts of graph-structured data in databases and data science platforms. FPGAs as accelerators for graph…

数据库 · 计算机科学 2021-02-09 Jonas Dann , Daniel Ritter , Holger Fröning

AI acceleration has been dominated by GPUs, but the growing need for lower latency, energy efficiency, and fine-grained hardware control exposes the limits of fixed architectures. In this context, Field-Programmable Gate Arrays (FPGAs)…

分布式、并行与集群计算 · 计算机科学 2025-11-18 Arturo Urías Jiménez

Mixed-precision neural networks (MPNNs) that enable the use of just enough data width for a deep learning task promise significant advantages of both inference accuracy and computing overhead. FPGAs with fine-grained reconfiguration…

硬件体系结构 · 计算机科学 2023-08-23 Erjing Luo , Haitong Huang , Cheng Liu , Guoyu Li , Bing Yang , Ying Wang , Huawei Li , Xiaowei Li

FPGA-based hardware accelerators have received increasing attention mainly due to their ability to accelerate deep pipelined applications, thus resulting in higher computational performance and energy efficiency. Nevertheless, the amount of…

分布式、并行与集群计算 · 计算机科学 2021-03-23 R. Nepomuceno , R. Sterle , G. Valarini , M. Pereira , H. Yviquel , G. Araujo

Macro placement is a critical phase in chip design, which becomes more intricate when involving general rectilinear macros and layout areas. Furthermore, macro placement that incorporates human-like constraints, such as design hierarchy and…

Efficient and real time segmentation of color images has a variety of importance in many fields of computer vision such as image compression, medical imaging, mapping and autonomous navigation. Being one of the most computationally…

计算机视觉与模式识别 · 计算机科学 2017-10-09 Roopal Nahar , Akanksha Baranwal , K. Madhava Krishna

In recent years, Convolutional Neural Networks (ConvNets) have become an enabling technology for a wide range of novel embedded Artificial Intelligence systems. Across the range of applications, the performance needs vary significantly,…

计算机视觉与模式识别 · 计算机科学 2017-11-27 Stylianos I. Venieris , Christos-Savvas Bouganis

Timing optimization during the global placement of integrated circuits has been a significant focus for decades, yet it remains a complex, unresolved issue. Recent analytical methods typically use pin-level timing information to adjust net…

硬件体系结构 · 计算机科学 2025-03-18 Yunqi Shi , Siyuan Xu , Shixiong Kai , Xi Lin , Ke Xue , Mingxuan Yuan , Chao Qian

The growing demand for efficient long-sequence modeling on edge devices has propelled widespread adoption of State Space Models (SSMs) like Mamba, due to their superior computational efficiency and scalability. As its autoregressive…

硬件体系结构 · 计算机科学 2025-09-25 Linfeng Zhong , Songqiang Xu , Huifeng Wen , Tong Xie , Qingyu Guo , Yuan Wang , Meng Li

Partial Reconfiguration (PR) is a technique that allows reconfiguring the FPGA chip at runtime. However, current design support tools require manual floorplanning of the partial modules. Several approaches have been proposed in this field,…

硬件体系结构 · 计算机科学 2019-04-25 Norbert Deak , Octavian Creţ , Horia Hedeşiu

In recent years, utilization of heterogeneous hardware other than small core CPU such as GPU, FPGA or many core CPU is increasing. However, when using heterogeneous hardware, barriers of technical skills such as OpenMP, CUDA and OpenCL are…

分布式、并行与集群计算 · 计算机科学 2021-07-13 Yoji Yamato

Despite the increasing adoption of Field-Programmable Gate Arrays (FPGAs) in compute clouds, there remains a significant gap in programming tools and abstractions which can leverage network-connected, cloud-scale, multi-die FPGAs to…

分布式、并行与集群计算 · 计算机科学 2024-02-05 Neha Prakriya , Yuze Chi , Suhail Basalama , Linghao Song , Jason Cong

Chip placement plays an important role in physical design. While generative models like diffusion models offer promising learning-based solutions, current methods have the following limitations: they use random synthetic data for…

硬件体系结构 · 计算机科学 2026-04-28 Peng Xie , Ke Xue , Yunqi Shi , Ruo-Tong Chen , Chengrui Gao , Siyuan Xu , Chenjian Ding , Mingxuan Yuan , Chao Qian

Placement is an essential task in modern chip design, aiming at placing millions of circuit modules on a 2D chip canvas. Unlike the human-centric solution, which requires months of intense effort by hardware engineers to produce a layout to…

计算机视觉与模式识别 · 计算机科学 2022-11-28 Yao Lai , Yao Mu , Ping Luo

In todays world, high-power computing applications such as image processing, digital signal processing, graphics, and robotics require enormous computing power. These applications use matrix operations, especially matrix multiplication.…

硬件体系结构 · 计算机科学 2019-10-29 Arish S , R. K. Sharma

Field-Programmable Gate Arrays (FPGAs) have asserted themselves as vital assets in contemporary computing by offering adaptable, reconfigurable hardware platforms. FPGA-based accelerators incubate opportunities for breakthroughs in areas,…

Global placement is a fundamental step in VLSI physical design. The wide use of 2D processing element (PE) arrays in machine learning accelerators poses new challenges of scalability and Quality of Results (QoR) for state-of-the-art…

硬件体系结构 · 计算机科学 2024-06-21 Andrew B. Kahng , Zhiang Wang
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