Chip placement plays an important role in physical design. While generative models like diffusion models offer promising learning-based solutions, current methods have the following limitations: they use random synthetic data for pre-training, require long sampling times, and often result in overlaps due to their dependence on gradient-based solvers during the sampling process. To overcome these issues, we propose FlowPlace, which features mask-guided synthetic data generation, flow-based efficient training with flexible prior injection, and hard constraint sampling for overlap-free layouts. Experiments on OpenROAD and ICCAD 2015 benchmarks show FlowPlace achieves better PPA metrics, 10-50× faster sampling efficiency, and zero overlaps.
@article{arxiv.2604.23658,
title = {FlowPlace: Flow Matching for Chip Placement},
author = {Peng Xie and Ke Xue and Yunqi Shi and Ruo-Tong Chen and Chengrui Gao and Siyuan Xu and Chenjian Ding and Mingxuan Yuan and Chao Qian},
journal= {arXiv preprint arXiv:2604.23658},
year = {2026}
}