相关论文: A 125$\mu$W 8kS/s Sub-pA Area-Efficient Current Se…

We developed a high-speed and low-noise time-domain current measurement scheme using a homemade GaAs high-electron-mobility-transistor-based cryogenic transimpedance amplifier (TIA). The scheme is versatile for broad cryogenic current…

This paper presents the first sub-10$\mu$W, sub-0.1% total harmonic distortion (THD) sinusoidal current generator (CG) integrated circuit (IC) that is capable of 20kHz output for the bio-impedance (Bio-Z) sensing applications. To benefit…

A 12 bit Pipeline ADC fabricated in a 0.18 $\mu$m pure digital CMOS technology is presented. Its nominal conversion rate is 110MS/s and the nominal supply voltage is 1.8V. The effective number of bits is 10.4 when a 10MHz input signal with…

The design and measurement results of ultra-low power, fast 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) prototypes in 65 nm CMOS technology are presented. Eight prototype ADCs were designed using two…

This paper proposes a low-power and low-noise instrumentation amplifier (IA) tailored for bioimpedance sensing applications. The design originates from a gain-boosted flipped voltage follower (FVF) transconductance (TC) stage and integrates…

The ubiquitous use of sensing and signal processing is increasing exponentially with the advance of the Internet of Everything (IoE). In this context, the design of every time more power efficient sensor nodes is a must. Within these nodes,…

This paper presents a low-power 10-bit 130-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 90 nm CMOS process. The proposed asynchronous ADC consists of a comparator, SAR logic block and two control blocks…

This paper presents a compact low-power, low-noise bioamplifier for multi-channel electrode arrays, aimed at recording action potentials. The design we put forth attains a notable decrease in both size and power consumption. This is…

We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital…

The purpose of this project was to design and implement a pipeline Analog-to-Digital Converter using 0.35um CMOS technology. Initial requirements of a 25-MHz conversion rate and 8-bits of resolution where the only given ones. Although…

This manuscript describes a radiation-hardened current-mode delta-sigma ADC fabricated in a standard 130 nm CMOS technology and qualified for total ionizing doses up to 100 Mrad. The operational signal range achieved with a 100 s…

This paper presents the design and analysis of a wearable CMOS biosensor with three different designs of energy-resolution scalable time-based resistance to digital converters (RDC), targeted towards either minimizing the energy/conversion…

This paper describes a pipelined analog-to-digital converter (ADC) employing a power and area efficient architecture. The adjacent stages of a pipeline share operational amplifiers. In order to keep accuracy of the amplifiers in the first…

In this paper the PreAmplifier ShAper (PASA) for the Time Projection Chamber (TPC) of the ALICE experiment at LHC is presented. The ALICE TPC PASA is an ASIC that integrates 16 identical channels, each consisting of Charge Sensitive…

Neuromorphic vision processor is an electronic implementation of vision algorithm processor on semiconductor. To image the world, a low-power CMOS image sensor array is required in the vision processor. The image sensor array is typically…

The proposed delta-sigma modulator ($\Delta\Sigma$M) based signal acquisition architecture uses a differential difference amplifier (DDA) customized for dual purpose roles, namely as instrumentation amplifier and as integrator of…

A pico-ampere sensitive electrochemical sensor signal acquisition chain consisting of a multi-channel bidirectional current-mirror based potentiostat and a multiplexed current-input delta-sigma ($\Delta \Sigma$) ADC is presented.…

We have developed a new capacitive transimpedance amplifier (CTIA) that can be operated at 2 K, and have good performance as readout circuits of astronomical far-infrared array detectors. The circuit design of the present CTIA consists of…

This paper presents a fully integrated second-order level-crossing sampling data converter for real-time data compression and feature extraction. Compared with level-sampling ADCs which sample at fixed voltage levels, the proposed circuits…

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on…