Web-Based Simulator of Superscalar RISC-V Processors

Jiri Jaros; Michal Majer; Jakub Horky; Jan Vavra

Web-Based Simulator of Superscalar RISC-V Processors

Hardware Architecture 2024-11-13 v1

Authors: Jiri Jaros , Michal Majer , Jakub Horky , Jan Vavra

Abstract

Mastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to grasp the fundamentals of superscalar RISC-V processors, HW/SW co-design and HPC optimization techniques. With customizable processor and memory architecture, full C compiler support, and detailed runtime statistics, this tool offers a comprehensive learning experience. Enjoy the convenience of a modern, web-based GUI to enhance your understanding and skills.

Keywords

computer architecture simulation compiler optimization

Cite

@article{arxiv.2411.07721,
  title  = {Web-Based Simulator of Superscalar RISC-V Processors},
  author = {Jiri Jaros and Michal Majer and Jakub Horky and Jan Vavra},
  journal= {arXiv preprint arXiv:2411.07721},
  year   = {2024}
}

Related papers

View all related →