English

Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures

Hardware Architecture 2024-07-08 v1

Abstract

We present several enhancements to the open-source ESP platform to support flexible and efficient on-chip communication for programmable accelerators in heterogeneous SoCs. These enhancements include 1) a flexible point-to-point communication mechanism between accelerators, 2) a multicast NoC that supports data forwarding to multiple accelerators simultaneously, 3) accelerator synchronization leveraging the SoC's coherence protocol, 4) an accelerator interface that offers fine-grained control over the communication mode used, and 5) an example ISA extension to support our enhancements. Our solution adds negligible area to the SoC architecture and requires minimal changes to the accelerators themselves. We have validated most of these features in complex FPGA prototypes and plan to include them in the open-source release of ESP in the coming months.

Keywords

Cite

@article{arxiv.2407.04182,
  title  = {Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures},
  author = {Joseph Zuckerman and John-David Wellman and Ajay Vanamali and Manish Shankar and Gabriele Tombesi and Karthik Swaminathan and Kevin Lee and Mohit Kapur and Robert Philhower and Pradip Bose and Luca P. Carloni},
  journal= {arXiv preprint arXiv:2407.04182},
  year   = {2024}
}

Comments

Appeared in the Sixth International Workshop on Domain Specific System Architecture (DOSSA-6)

R2 v1 2026-06-28T17:29:39.431Z