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Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience

Hardware Architecture 2024-12-31 v1 Neural and Evolutionary Computing Signal Processing

Abstract

Since 2013, the PULP (Parallel Ultra-Low Power) Platform project has been one of the most active and successful initiatives in designing research IPs and releasing them as open-source. Its portfolio now ranges from processor cores to network-on-chips, peripherals, SoC templates, and full hardware accelerators. In this article, we focus on the PULP experience designing heterogeneous AI acceleration SoCs - an endeavour encompassing SoC architecture definition; development, verification, and integration of acceleration IPs; front- and back-end VLSI design; testing; development of AI deployment software.

Keywords

Cite

@article{arxiv.2412.20391,
  title  = {Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience},
  author = {Francesco Conti and Angelo Garofalo and Davide Rossi and Giuseppe Tagliavini and Luca Benini},
  journal= {arXiv preprint arXiv:2412.20391},
  year   = {2024}
}

Comments

Preprinted submitted to IEEE Solid-State Circuits Magazine

R2 v1 2026-06-28T20:51:00.630Z