Computing elements of CPSs must be flexible to ensure interoperability; and adaptive to cope with the evolving internal and external state, such as battery level and critical tasks. Cryptography is a common task needed in CPSs to guarantee private communication among different devices. In this work, we propose a reconfigurable FPGA accelerator for AES workloads with different key lengths. The accelerator architecture exploits tagged-dataflow models to support the concurrent execution of multiple threads on the same accelerator. This solution demonstrates to be more resource- and energy-efficient than a set of non-reconfigurable accelerators while keeping high performance and flexibility of execution.
@article{arxiv.2306.10788,
title = {A multithread AES accelerator for Cyber-Physical Systems},
author = {Francesco Ratto and Luigi Raffo and Francesca Palumbo},
journal= {arXiv preprint arXiv:2306.10788},
year = {2023}
}
Comments
6 pages. It will appear in 20th ACM International Conference on Computing Frontiers (CF 23), May 9 to 11, 2023, Bologna, Italy