乘法器：基于傅里叶变换方法与 Synopsys 设计技术在常规与饱和算术下最高 32 位输入的比较
硬件体系结构
2016-11-17 v1
摘要
本文介绍了一种基于傅里叶变换的硬件乘法技术。该技术在最高 8 位范围的乘法单元上具有最高效率。每个乘法单元均基于最小化布尔函数实现。实验数据表明，与采用 Synopsys 技术设计的同类产品相比，该技术在 2-8 位输入操作数范围内可将乘法过程速度提升高达 20%，在 8-32 位输入操作数范围内提升高达 3%。
引用
@article{arxiv.1611.05415,
title = {Multipliers: comparison of Fourier transformation based method and Synopsys design technique for up to 32 bits inputs in regular and saturation arithmetics},
author = {Danila Gorodecky},
journal= {arXiv preprint arXiv:1611.05415},
year = {2016}
}
备注
Proceedings of the 12th International Workshop on Boolean Problems, Freiberg, Germany, Sept. 22-23, 2016. Edited by B. Steinbach. Freiberg University of Mining and Technology. P. 145-150. Changed title from "Multipliers design technique based disjunctive normal form minimizationa and Fourier transformation"; fixed some inaccuracies