Epiphany架构上信号处理系统的延迟优化
分布式、并行与集群计算
2015-12-18 v1
摘要
在本文中，我们使用Adapteva Epiphany多核芯片来展示如何通过任务并行化、数据并行化以及数据流水线的组合，优化通常在LTE或WiFi中发现的基带信号处理链的通吞吐量和延迟。Epiphany的共享内存架构以及一个核上的处理器可直接写入片上任何其他核的内存这一事实，促进了并行化和数据流水线。
引用
@article{arxiv.1512.05578,
title = {Improving Latency in a Signal Processing System on the Epiphany Architecture},
author = {Peter Brauer and Martin Lundqvist and Aare Mällo},
journal= {arXiv preprint arXiv:1512.05578},
year = {2015}
}
备注
Draft paper submitted to and accepted by PDP 2016, 24th Euromicro International Conference on Parallel, Distributed and Network-Based Processing. Heraklion Crete, Greece, 17th-19th February 2016