具有序列重复节点的高吞吐快速SSC极化译码器实现
信息论
2020-08-20 v2 math.IT
摘要
尽管极化码已被最新 5G 蜂窝标准采纳,其仍面临解码时延高的根本问题。为解决该问题,近期文献 \cite{sr2020} 提出了基于新型序列重复(SR)节点类的快速简化连续消除(Fast-SSC)译码器,理论上其所需时间步数少于其他现有 Fast-SSC 译码器。本文聚焦于该基于 SR 节点的快速 SSC(SRFSC)译码器的硬件实现。针对长度 1024、码率 1/2 的极化码,实现结果显示我们的实现在 Altera Stratix IV FPGA 上达到 Mbps 吞吐量,较先前工作提高 17.9%。
引用
@article{arxiv.2007.11394,
title = {Implementation of a High-Throughput Fast-SSC Polar Decoder with Sequence Repetition Node},
author = {Haotian Zheng and Alexios Balatsoukas-Stimming and Zizheng Cao and Ton Koonen},
journal= {arXiv preprint arXiv:2007.11394},
year = {2020}
}
备注
6 pages, 6 figures. Accepted and to appear in IEEE International Workshop on Signal Processing Systems, Oct 2020 (SIPS2020). The latest version. arXiv admin note: text overlap with arXiv:2005.04394