Arrow: A RISC-V Vector Accelerator for Machine Learning Inference

Imad Al Assir; Mohamad El Iskandarani; Hadi Rayan Al Sandid; Mazen A. R. Saghir

Arrow: A RISC-V Vector Accelerator for Machine Learning Inference

Hardware Architecture 2021-07-16 v1

Authors: Imad Al Assir , Mohamad El Iskandarani , Hadi Rayan Al Sandid , Mazen A. R. Saghir

Abstract

In this paper we present Arrow, a configurable hardware accelerator architecture that implements a subset of the RISC-V v0.9 vector ISA extension aimed at edge machine learning inference. Our experimental results show that an Arrow co-processor can execute a suite of vector and matrix benchmarks fundamental to machine learning inference 2 - 78x faster than a scalar RISC processor while consuming 20% - 99% less energy when implemented in a Xilinx XC7A200T-1SBG484C FPGA.

Keywords

computer architecture fpga accelerator

Cite

@article{arxiv.2107.07169,
  title  = {Arrow: A RISC-V Vector Accelerator for Machine Learning Inference},
  author = {Imad Al Assir and Mohamad El Iskandarani and Hadi Rayan Al Sandid and Mazen A. R. Saghir},
  journal= {arXiv preprint arXiv:2107.07169},
  year   = {2021}
}

Comments

Presented at the Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021), co-located with ISCA 2021

Related papers

View all related →