具形式误差界的混合残差浮点数值架构用于高吞吐FPGA计算

浮点运算在FPGA平台上代价高昂，由于宽数据路径、归一化和进位传递，催生了提高吞吐和效率的替代数值表示。本文提出混合残差浮点数值架构(HRFNA)，这是一种完全指定的数值系统，将无携带残差算术与轻量级指数基准缩放相结合，以实现宽动态范围、可预测的误差行为和高效FPGA实现。HRFNA在严格的数学基础下开发：形式定义混合数空间，证明算术和归一化的正确性，并导出显式绝对和相对误差界，将舍入限制在不频繁的归一化事件中。 presented a complete FPGA microarchitecture, featuring deeply pipelined modular arithmetic, exponent management, and a CRT-based normalization engine that sustains an initiation interval of one cycle under steady-state operation. Application-level evaluation on dot products, dense matrix multiplication, and iterative Runge-Kutta ODE solvers demonstrates stable numerical behavior over long computation sequences. Implemented on a Xilinx Zynq UltraScale Plus ZCU104, HRFNA achieves up to 2.4 times higher throughput, 38 to 55 percent LUT reduction, and up to 1.9 times energy efficiency improvement compared to IEEE 754 FP32 baselines, while maintaining bounded numerical error. Comparative analysis shows that HRFNA occupies a previously unexplored design point between numerical stability, dynamic range, and hardware efficiency, making it well suited for FPGA-centric scientific and CAD-relevant computation.