Related papers: Reduced Area Low Power High Throughput BCD Adders …
A new subcarrier combining technique is proposed for MC -CDMA receiver in mobile Rayleigh fading channel. It exploits the structure formed by repeating spreading sequences of users on different subcarriers to simultaneously suppress…
This article presents the design of a new asynchronous early output full adder which when cascaded leads to a relative-timed ripple carry adder (RCA). The relative-timed RCA requires imposing a very small relative-timing assumption to…
Today every circuit has to face the power consumption issue for both portable device aiming at large battery life and high end circuits avoiding cooling packages and reliability issues that are too complex. It is generally accepted that…
Due to the power consumption and high circuit cost in antenna arrays, the practical application of massive multiple-input multiple-output (MIMO) in the sixth generation (6G) and future wireless networks is still challenging. Employing…
A tapered floating point encoding is proposed which uses the redundant signed radix 2 system and is based on the canonical recoding. By making use of ternary technology, the encoding has a dynamic range exceeding that of the…
Scalability and modularity are key features for future power converters, such that these systems can be easily employed in many applications with different electrical specifications. In this thesis, the potential of a new bidirectional…
The demand for low power processing is increasing due to mobile and portable devices. In a processor unit, an adder is an important building block since it is used in Floating Point Units (FPU) and Arithmetic Logic Units (ALU). Also,…
Transversal gates are the ideal gates in a fault-tolerant scenario; relatively easy to implement, and minimally error propagating. Their availability will maximise fault tolerant thresholds, enabling universal quantum computation in a wider…
The main areas of research in VLSI system design include area, high speed, and power-efficient data route logic systems. The amount of time needed to send a carry through the adder limits the pace at which addition can occur in digital…
Recent bilinear feed-forward replacements for vision transformers can substantially improve accuracy, but they often conflate two effects: stronger second-order interactions and increased redundancy relative to the main branch. We study a…
This paper presents a ternary half adder and a 1-trit multiplier using carbon nanotube transistors. The proposed circuits are designed using pass transistor logic and dynamic logic. Ternary logic uses less connections than binary logic, and…
Control modular addition is a core arithmetic function, and we must consider the computational cost for actual quantum computers to realize efficient implementation. To achieve a low computational cost in a control modular adder, we focus…
Due to high power consumption and difficulties with minimizing the CMOS transistor size, molecular electronics has been introduced as an emerging technology. Further, there have been noticeable advances in fabrication of molecular wires and…
The 4th Concept detector presently being designed for the International Linear Collider introduces several innovations in order to achieve the necessary experimental goal of a detecter that is 2-to-10 times better than the already excellent…
The rapid adoption of low-precision arithmetic in artificial intelligence and edge computing has created a strong demand for energy-efficient and flexible floating-point multiply-accumulate (MAC) units. This paper presents a dual-precision…
A new Schottky-gate Bipolar Mode Field Effect Transistor (SBMFET) is proposed and verified by two-dimensional simulation. Unlike in the case of conventional BMFET, which uses deep diffused p+-regions as the gate, the proposed device uses…
A modular, programmable, and high performance Power Gating strategy, called cluster based tunable sleep transistor cell Power Gating, has been introduced in the present paper with a few modifications. Furthermore, a detailed comparison of…
Transformer models have revolutionized AI tasks, but their large size hinders real-world deployment on resource-constrained and latency-critical edge devices. While binarized Transformers offer a promising solution by significantly reducing…
In this letter, we present a novel four-way divider/combiner in rectangular waveguide. The design is completely two-dimensional in the h-plane, with eight-fold mirror symmetry, and is based on a recent four-port hybrid design [6]. In…
This paper describes the new concept of the double-LGAD. The goal is to increase the charge at the input of the electronics, keeping a time resolution equal or better than a standard (single) LGAD; this has been realized by adding the…