Related papers: Reduced Area Low Power High Throughput BCD Adders …

In this paper, we propose an all-optical high-speed half adder based on linear defects in a photonic crystal (PhC) structure composed of silicon rods. The proper design of half adder results in no need to increase the intensity of the input…

We present a new linear-depth ripple-carry quantum addition circuit. Previous addition circuits required linearly many ancillary qubits; our new adder uses only a single ancillary qubit. Also, our circuit has lower depth and fewer gates…

Quantum computing (QC) requires cryogenic electronic circuits as control and readout sub-systems of quantum chips to meet the qubit scale-up challenges.At this temperature,MOSFETs transistors exhibition many changes such as higher threshold…

The Dadda algorithm is a parallel structured multiplier, which is quite faster as compared to array multipliers, i.e., Booth, Braun, Baugh-Wooley, etc. However, it consumes more power and needs a larger number of gates for hardware…

Qudit-based quantum gates offer several advantages over qubit-based counterparts, such as higher information density, the ability to address more complex problems, and richer quantum operations. In this paper, we present three realistic…

In this paper, we propose a new class of bit flipping algorithms for low-density parity-check (LDPC) codes over the binary symmetric channel (BSC). Compared to the regular (parallel or serial) bit flipping algorithms, the proposed…

A novel architecture of the center-fed pinching antenna system (C-PASS) is proposed. In contrast to the conventional end-fed PASS, signals are fed from the center input ports and propagate towards both sides of the waveguide. By doing so,…

The search for a compatible application of memristor-CMOS logic gates has remained elusive, as the data density benefits are offset by slow switching speeds and resistive dissipation. Active microdisplays typically prioritize pixel density…

In this paper, we demonstrate by simulation the general usability of an electrostatically doped and electrically reconfigurable planar field-effect transistor (FET) structure. The device concept is partly based on our already published and…

A low-power Content-Addressable-Memory (CAM) is introduced employing a new mechanism for associativity between the input tags and the corresponding address of the output data. The proposed architecture is based on a recently developed…

Reversible logic design has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power CMOS design, digital signal processing and nanotechnology.…

The complementary field-effect transistors (CFETs), featuring vertically stacked n/p-FETs, enhance integration density and significantly reduce the area of standard cells such as static random-access memory (SRAM). However, the advantage of…

In this paper, a circuit employing current controlled current conveyor trans-conductance amplifiers (CCCCTAs) as active element is proposed which can function both as biquad filter and oscillator. It uses two CCCCTAs and two capacitors. As…

Grant-free multiple-access (GFMA) is a valuable research topic, since it can support multiuser transmission with low latency. This paper constructs novel uniquely-decodable multi-amplitude sequence (UDAS) sets for GFMA systems, which can…

This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at 180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock frequency as compared to single edge triggered…

In this paper, we have experimentally demonstrated, for the first time, III-V 4D transistors with vertically stacked InGaAs nanowire (NW) channels and gate-all-around (GAA) architecture. Novel process technology enabling the transition from…

A four-stage operational transconductance amplifier (OTA) for ultra-low-power applications is introduced in this paper. The proposed circuit inclusive of frequency compensation requires minimal transistor count and passives, overcoming the…

We propose the use of a lower or upper triangular sub-base matrix to replace the identity matrix in the source-check-channel-variable linking protomatrix of a double-protograph low-density parity-check joint-source-channel code (DP-LDPC…

A new TDC-chip is under development for the COMPASS experiment at CERN. The ASIC, which exploits the 0.6 micrometer CMOS sea-of-gate technology, will allow high resolution time measurements with digitization of 75 ps, and an unprecedented…

A sub-excitable BZ medium responds to asymmetric local perturbation by producing travelling localised excitation wave-fragments, distant relatives of dissipative solitons. The size and life span of an excitation wave-fragment depend on the…