Related papers: Reduced Area Low Power High Throughput BCD Adders …
Traditionally, the output noise and power supply rejection of low-dropout regulators (LDOs) are optimized to minimize power supply fluctuations, reducing their impact on the low-frequency noise of target voltage-controlled oscillators…
Charge-coupled device (CCD), along with the complementary metal-oxide-semiconductor (CMOS), is one of the major imaging technologies. Traditional CCDs rely on the charge transfer between potential wells, which gives them advantages of…
Low-power designs are a necessity with the increasing demand of portable devices which are battery operated. In many of such devices the operational speed is not as important as battery life. Logic-in-memory structures using nano-devices…
In this paper, we formulate a new problem to cope with the transmission of extra bits over an existing coded transmission link (referred to as coded payload link) without any cost of extra transmission energy or extra bandwidth. This is…
Non-Gaussian quantum gates are essential components for optical quantum information processing. However, the efficient implementation of practically important multi-mode higher-order non-Gaussian gates has not been comprehensively studied.…
A novel readout architecture that uses multiple non-destructive floating-gate amplifiers to achieve sub-electron readout noise in a thick, fully-depleted silicon detector is presented. This Multi-Amplifier Sensing Charge-Coupled Device…
A comprehensive review and fair comparison of previous priority encoder (PE) designs over the past one and a half decades are presented using a 45 nm technology. Further, potential limitations of existed PEs are identified, based on which…
Memristor has been identified as the fourth fundamental circuit element by Dr. Leon Chua in 1971 and since then it has gathered a lot of interest because of its non-volatility and are considered as a viable solution to the beyond CMOS era…
This paper reports the last technological development on the Low Gain Avalanche Detector (LGAD) and introduces a new architecture of these detectors called inverse-LGAD (iLGAD). Both approaches are based on the standard Avalanche Photo…
Recently, optical bound states in continuum in various passive photonic crystals have been identified and similar structures incorporated with optical gain have been reported to exhibit lasing. However, no explicit control over the type of…
Charge Coupled Devices (CCDs) have been successfully used in several high energy physics experiments over the past two decades. Their high spatial resolution and thin sensitive layers make them an excellent tool for studying short-lived…
We first show how to construct an O(n)-depth O(n)-size quantum circuit for addition of two n-bit binary numbers with no ancillary qubits. The exact size is 7n-6, which is smaller than that of any other quantum circuit ever constructed for…
Multi-valued logic gates, which can handle quaternary numbers as inputs, are developed by exploiting the ballistic transport properties of quantum point contacts in series. The principle of a logic gate that finds the minimum of two…
Scaling up quantum computing hardware is hindered by the narrow operating margins of current quantum components. Here, we introduce a composite qubit and gate scheme that achieves wide margins by use of transistor-like nonlinearities to…
This contribution presents the design, production, and initial testing of newly developed 4H-SiC Low Gain Avalanche Detectors (LGADs). The evaluation includes performance metrics such as the internal gain layer's efficiency in enhancing…
Quantum addition circuits are considered being of two types: 1) Toffolli-adder circuits which use only classical reversible gates (CNOT and Toffoli), and 2) QFT-adder circuits based on the quantum Fourier transformation. We present the…
In this report, a new fuzzy 2bit-AND parallel-to-OR, or simply, a fuzzy binary AND/OR (FBAR) text data compression model as an algorithm is suggested for bettering spatial locality limits on nodes during database transactions. The current…
This paper describes a pipelined analog-to-digital converter (ADC) employing a power and area efficient architecture. The adjacent stages of a pipeline share operational amplifiers. In order to keep accuracy of the amplifiers in the first…
Protograph-based, off-the-shelf low-density parity-check (LDPC) codes are optimized for higher-order modulation and quantized sum-product decoders. As an example, for the recently proposed LDPC code from the upcoming IEEE 802.3ca standard…
This PhD dissertation investigates garbage-free reversible computing systems from abstract design to physical gate-level implementation. Designed in reversible logic, we propose a ripple-block carry adder and work towards a reversible…