Related papers: Reduced Area Low Power High Throughput BCD Adders …

Recently, we proposed a novel transistor architecture for 3D stacked FETs called Flip FET (FFET), featuring N/P transistors back-to-back stacked and dual-sided interconnects. With dual-sided power rails and signal tracks, FFET can achieve…

A novel design-friendly device called the transistor-injected dual doping quantum cascade laser (TI-D2QCL) with two different doping in each stack of a homogeneous superlattice is proposed. By adjusting the base-emitter bias Vbe of the…

Fast binary compressors are the main components of many basic digital calculation units. In this paper, a high-speed (7,2) compressor with a fast carry-generation logic is proposed. The carry-generation logic is based on the sorting…

Ferroelectric field effect transistor (FeFET) memory has shown the potential to meet the requirements of the growing need for fast, dense, low-power, and non-volatile memories. In this paper, we propose a memory architecture named…

Spectral analysis plays an important role in detection of damage in structures and deep learning. The choice of a floating-point format plays a crucial role in determining the accuracy and performance of spectral analysis. The IEEE Std…

We report on the development of InP-based semiconductor amplifiers with a U-bend waveguide geometry having the input and output ports on one facet only. This waveguide geometry simplifies the chip alignment during the hybrid integration on…

In this paper we analyze the performance of several bit-interleaving strategies applied to Non-Binary Low-Density Parity-Check (LDPC) codes over the Rayleigh fading channel. The technique of bit-interleaving used over fading channel…

This paper presents an approximate signed multiplier architecture that incorporates a sign-focused compressor, specifically designed for edge detection applications in machine learning and signal processing. The multiplier incorporates two…

Three-dimensional topological insulators are characterized by the presence of a bandgap in their bulk and gapless Dirac fermions at their surfaces. New physical phenomena originating from the presence of the Dirac fermions are predicted to…

Most of the work on implementing arithmetic on a quantum computer has borrowed from results in classical reversible computing (e.g. [VBE95], [BBF02], [DKR04]). These quantum networks are inherently classical, as they can be implemented with…

The basic building blocks for Resonant Tunnelling Diode (RTD) logic circuits are Threshold Gates (TGs) instead of the conventional Boolean gates (AND, OR, NAND, NOR) due to the fact that, when designing with RTDs, threshold gates can be…

The commercialization of transistors capable of both switching and amplification in 1960 resulted in the development of second-generation computers, which resulted in the miniaturization and lightening, while accelerating the reduction and…

In this work, we report implementation and performance evaluation of memristor-driven fundamental logic gates, including NOT, AND, NAND, OR, NOR, and XOR, and novel and optimized design of the sequential logic circuits, such as D flip-flop,…

Industrial PID consists of three elements: Lag (integrator), Lead (Differentiator) and Low Pass Filters (LPF). PID being a linear control method is inherently bounded by the waterbed effect due to which there exists a trade-off between…

The increasing share of converter based resources in power systems calls for scalable methods to analyse stability without relying on exhaustive system wide simulations. Decentralized small gain and small-phase criteria have recently been…

Charge Coupled Devices (CCDs) have been successfully used in several high energy physics experiments over the past two decades. Their high spatial resolution and thin sensitive layers make them an excellent tool for studying short-lived…

It is well known that a nontrivial Chern number results in quantized Hall conductance. What is less known is that, generically, the Hall response can be dramatically different from its quantized value in materials with broken inversion…

The design of gate drivers is an important topic in power converter topologies that can help reduce switching losses and increase power density. Gate driving techniques that offer zero-voltage switching and/or zero current switching have…

This paper presents design techniques for an energy-efficient multi-lane receiver (RX) with baud-rate clock and data recovery (CDR), which is essential for high-throughput low-latency communication in high-performance computing systems. The…

The Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful…