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While general-purpose computing follows Von Neumann's architecture, the data movement between memory and processor elements dictates the processor's performance. The evolving compute-in-memory (CiM) paradigm tackles this issue by…

Hardware Architecture · Computer Science 2024-11-15 Dhandeep Challagundla , Ignatius Bezzam , Riadul Islam

Data movement in memory-intensive workloads, such as deep learning, incurs energy costs that are over three orders of magnitude higher than the cost of computation. Since these workloads involve frequent data transfers between memory and…

Hardware Architecture · Computer Science 2025-02-05 Bahareh Khabbazan , Marc Riera , Antonio González

The speed of modern digital systems is severely limited by memory latency (the ``Memory Wall'' problem). Data exchange between Logic and Memory is also responsible for a large part of the system energy consumption. Logic--In--Memory (LiM)…

Hardware Architecture · Computer Science 2023-04-14 Fabrizio Ottati , Giovanna Turvani , Marco Vacca , Guido Masera

Cache fusion accelerates generation process of LLMs equipped with RAG through KV caching and selective token recomputation, thereby reducing computational costs and improving efficiency. However, existing methods primarily rely on local…

Databases · Computer Science 2026-04-13 Jianxin Yan , Zeheng Qian , Wangze Ni , Zhitao Shen , Zhiping Wang , Haoyang Li , Jia Zhu , Lei Chen , Kui Ren

Processing-in-memory (PIM) has emerged as a promising solution for accelerating memory-intensive workloads as they provide high memory bandwidth to the processing units. This approach has drawn attention not only from the academic community…

Hardware Architecture · Computer Science 2024-09-11 Dongjae Lee , Bongjoon Hyun , Taehun Kim , Minsoo Rhu

Compute-In-Memory (CIM) systems, particularly those utilizing ReRAM and memristive technologies, offer a promising path toward energy-efficient neural network computation. However, conventional quantization and compression techniques often…

Hardware Architecture · Computer Science 2025-12-23 Guan-Cheng Chen , Chieh-Lin Tsai , Pei-Hsuan Tsai , Yuan-Hao Chang

Large language models (LLMs) have recently transformed natural language processing, enabling machines to generate human-like text and engage in meaningful conversations. This development necessitates speed, efficiency, and accessibility in…

Hardware Architecture · Computer Science 2024-06-13 Christopher Wolters , Xiaoxuan Yang , Ulf Schlichtmann , Toyotaro Suzumura

Self-attention in Transformers generates dynamic operands that force conventional Compute-in-Memory (CIM) accelerators into costly non-volatile memory (NVM) reprogramming cycles, degrading throughput and stressing device endurance. Existing…

Hardware Architecture · Computer Science 2026-04-10 Md Zesun Ahmed Mia , Jiahui Duan , Kai Ni , Abhronil Sengupta

SRAM-based compute-in-memory (CIM) offers high computational density and energy efficiency for deep neural network (DNN) accelerators, but its limited capacity causes on/off-chip data movement overhead for large DNN models. Existing CIM…

Hardware Architecture · Computer Science 2026-04-21 Chenhao Xue , Yukun Wang , An Guo , Yuhui Shi , Jinwei Zhou , Xiping Dong , Yihan Yin , Yuanpeng Zhang , Tianyu Jia , Wei Gao , Qiang Wu , Xin Si , Jun Yang , Guangyu Sun

Computing-in-Memory (CiM) architectures aim to reduce costly data transfers by performing arithmetic and logic operations in memory and hence relieve the pressure due to the memory wall. However, determining whether a given workload can…

Hardware Architecture · Computer Science 2020-01-16 Di Gao , Dayane Reis , Xiaobo Sharon Hu , Cheng Zhuo

Conventional LLM inference architectures suffer from high energy and latency due to frequent data movement across memory hierarchies. We propose Ouroboros, a wafer-scale SRAM-based Computing-in-Memory (CIM) architecture that executes all…

Hardware Architecture · Computer Science 2026-03-04 Yiqi Liu , Yudong Pan , Mengdi Wang , Shixin Zhao , Haonan Zhu , Yinhe Han , Lei Zhang , Ying Wang

This paper introduces SpeedLLM, a neural network accelerator designed on the Xilinx Alevo U280 platform and optimized for the Tinyllama framework to enhance edge computing performance. Key innovations include data stream parallelism, a…

Hardware Architecture · Computer Science 2025-07-22 Peipei Wang , Wu Guan , Liping Liang , Zhijun Wang , Hanqing Luo , Zhibin Zhang

The rise of data-intensive applications exposed the limitations of conventional processor-centric von-Neumann architectures that struggle to meet the off-chip memory bandwidth demand. Therefore, recent innovations in computer architecture…

Hardware Architecture · Computer Science 2024-05-28 Asif Ali Khan , Hamid Farzaneh , Karl F. A. Friebel , Clément Fournier , Lorenzo Chelini , Jeronimo Castrillon

In this paper, we propose LoopLynx, a scalable dataflow architecture for efficient LLM inference that optimizes FPGA usage through a hybrid spatial-temporal design. The design of LoopLynx incorporates a hybrid temporal-spatial architecture,…

Hardware Architecture · Computer Science 2025-04-15 Jianing Zheng , Gang Chen

Compute-in-memory (CIM) accelerators for spiking neural networks (SNNs) are promising solutions to enable $\mu$s-level inference latency and ultra-low energy in edge vision applications. Yet, their current lack of flexibility at both the…

Hardware Architecture · Computer Science 2024-10-31 Nicolas Chauvaux , Adrian Kneip , Christoph Posch , Kofi Makinwa , Charlotte Frenkel

Large Language Models (LLMs) such as LLaMA and DeepSeek, are built on transformer architectures, which have become a standard model for achieving state-of-the-art performance in natural language processing tasks. Recently, there has been…

Hardware Architecture · Computer Science 2026-04-21 Bas Ahn , Xingjian Tao , Manil Dev Gomony , Marc Geilen , Henk Corporaal

The deployment of large language models (LLMs) presents significant challenges due to their enormous memory footprints, low arithmetic intensity, and stringent latency requirements, particularly during the autoregressive decoding stage.…

Hardware Architecture · Computer Science 2025-11-03 Cenlin Duan , Jianlei Yang , Rubing Yang , Yikun Wang , Yiou Wang , Lingkun Long , Yingjie Qi , Xiaolin He , Ao Zhou , Xueyan Wang , Weisheng Zhao

Decoder-only Transformer models such as GPT have demonstrated exceptional performance in text generation, by autoregressively predicting the next token. However, the efficacy of running GPT on current hardware systems is bounded by low…

Hardware Architecture · Computer Science 2024-04-16 Yuting Wu , Ziyu Wang , Wei D. Lu

Today's computing systems require moving data back-and-forth between computing resources (e.g., CPUs, GPUs, accelerators) and off-chip main memory so that computation can take place on the data. Unfortunately, this data movement is a major…

Hardware Architecture · Computer Science 2022-05-31 Geraldo F. Oliveira , Amirali Boroumand , Saugata Ghose , Juan Gómez-Luna , Onur Mutlu

Computing-In-Memory (CIM) offers a potential solution to the memory wall issue and can achieve high energy efficiency by minimizing data movement, making it a promising architecture for edge AI devices. Lightweight models like MobileNet and…

Hardware Architecture · Computer Science 2025-08-21 Choongseok Song , Doo Seok Jeong