Related papers: TSPC-PFD: TSPC-Based Low-Power High-Resolution CMO…

Partial discharge (PD) is a common indication of faults in power systems, such as generators, and cables. These PD can eventually result in costly repairs and substantial power outages. PD detection traditionally relies on hand-crafted…

We present a readout chip prototype for future pixel detectors with timing capabilities. The prototype is intended for characterizing 4D pixel arrays with a pixel size of $100\times100~\mu \text{m}^2$, where the sensors are Low Gain…

We theoretically investigate the temperature-to-phase conversion (TPC) process occurring in dc superconducting quantum interferometers based on superconductor--normal metal--superconductor (SNS) mesoscopic Josephson junctions. In…

Rapid single-flux quantum (RSFQ) is one of the most advanced superconductive electronics technologies. SFQ systems operate at tens of gigahertz with up to three orders of magnitude smaller power as compared to CMOS. In conventional SFQ…

This paper introduces a conversion matrix method for linear periodically time-variant (LPTV) digital phase-locked loop (DPLL) phase noise modeling that offers precise and computationally efficient results to enable rapid design iteration…

The design and performance of wave union TDC implemented in a Lattice CertusPro-NX FPGA is discussed. This FPGA is available for radiation tolerant applications. The TDC is implemented with 16-channels and a 200 MHz reference clock. Each…

We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power…

For future wireless communication technologies, an increase in capabilities such as throughput is strongly expected. Transmission in the sub-THz bands (>90 GHz) seems to be the potential solution to meet the ever-increasing capacity demands…

This paper presents a system-level analytical framework for modeling and minimizing phase noise in body-biased cross-coupled LC-tank voltage-controlled oscillators (LC-VCOs). Building upon Impulse Sensitivity Function (ISF) theory, the…

We propose a method to track signals from quadrant photodiodes (QPD) in heterodyne laser interferometers that employ digital phase-locked loops for phase readout. Instead of separately tracking the four segments from the QPD and then…

The ability to manipulate cavity resonant modes is of critical importance in laser physics and applications. By exploiting the parity time (PT) symmetry, we propose and experimentally realize a single-mode FP laser with improved output…

We developed a time-correlated single-photon counting (TCSPC) system based on the low-jitter superconducting nanowire single-photon detection (SNSPD) technology. The causes of jitters in the TCSPC system were analyzed. Owing to the low…

We present an experimental realization of the Optical Frequency Locked Loop (OFLL) applied to long-term frequency difference stabilization of broad-line DFB lasers. The presented design, based on an integrated phase-frequency detector chip,…

Location of non-stationary forced oscillation (FO) sources can be a challenging task, especially in cases under resonance condition with natural system modes, where the magnitudes of the oscillations could be greater in places far from the…

Charge Coupled Devices (CCDs) have been successfully used in several high energy physics experiments over the past two decades. Their high spatial resolution and thin sensitive layers make them an excellent tool for studying short-lived…

Differing from synchronous generators, there are lack of physical laws governing the synchronization dynamics of voltage-source converters (VSCs). The widely used phase-locked loop (PLL) plays a critical role in maintaining the synchronism…

Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC…

We describe a low-cost system designed to monitor wander in digital clocks with a precision of $\le$ 1 ps. With this system we have shown that it is possible to track phase variations at the sub-picosecond level by adding noise to a…

Face detection, as a fundamental technology for various applications, is always deployed on edge devices which have limited memory storage and low computing power. This paper introduces a Light and Fast Face Detector (LFFD) for edge…

Phase-locked loop (PLL), conceived in 1932 by H. Bellescize, has been the basic electronic component in the development of communication technology from the early analog radio receptors to modern digital civil and military facilities.…