Related papers: TSPC-PFD: TSPC-Based Low-Power High-Resolution CMO…

A high-resolution time-to-digital converter (TDC) based on wave union (four-edge WU A), dual-sampling, and sub-TDL methods is proposed and implemented in a 16-nm Xilinx UltraScale+ field-programmable gate array (FPGA). We combine WU and…

This paper presents a partially parallel low-density parity-check (LDPC) decoder designed for the 5G New Radio (NR) standard. The design is using a multi-block parallel architecture with a flooding schedule. The decoder can support any code…

Existing sub-/super-synchronous (SSO) suppression methods for the direct-drive permanent magnet synchronous generators (D-PMSG) integrated power systems are mainly achieved by external devices or sub-synchronous resonance damping controller…

In modern low-power embedded platforms, floating-point (FP) operations emerge as a major contributor to the energy consumption of compute-intensive applications with large dynamic range. Experimental evidence shows that 50% of the energy…

A simulation of an atomic force microscope operating in the constant amplitude dynamic mode is described. The implementation mimics the electronics of a real setup including a digital phase-locked loop (PLL). The PLL is not only used as a…

We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the…

We present a real-time differential phasefront detector sensitive to better than 3 mrad rms, which corresponds to a precision of about 500 pm. This detector performs a spatially resolving measurement of the phasefront of a heterodyne…

We have developed a completely new type of general-purpose CCD data acquisition system which enables one to drive any type of CCD using any type of clocking mode. A CCD driver system widely used before consisted of an analog multiplexer…

This paper presents a mixed-mode delay-locked loop (MM-DLL) with binary search (BS) locking, designed to cover a broad frequency range from 533 MHz to 4.26 GHz. The BS locking scheme optimizes the locking time, reducing it from a linear to…

The detection and characterization of partial discharge (PD) are crucial for the insulation diagnosis of overhead lines with covered conductors. With the release of a large dataset containing thousands of naturally obtained high-frequency…

Photonic integrated circuits (PICs) have emerged as a scalable platform for complex quantum technologies using photonic and atomic systems. A central goal has been to integrate photon-resolving detectors to reduce optical losses, latency,…

With the new generation of the RPC, it is possible to work with induced signals of hundreds $\mu V$, hence the front-end electronics is an important and delicate part of the detector in order to get a detectable signal. The electronic chain…

Software Defined Radio (SDR) platforms are valuable for research and development activities or high-end systems that demand real-time adaptable wireless protocols. While low latency can be achieved using the dedicated digital processing…

Clock generation is an essential part of wireless or wireline communication modules. To facilitate recent advancements in wireline-like communication and in-sensor computing modules at relatively lower data rates, ultra-low power, and…

The exponential emergence of Field Programmable Gate Array (FPGA) has accelerated the research of hardware implementation of Deep Neural Network (DNN). Among all DNN processors, domain specific architectures, such as, Google's Tensor…

Energy efficiency is becoming increasingly important for computing systems, in particular for large scale HPC facilities. In this work we evaluate, from an user perspective, the use of Dynamic Voltage and Frequency Scaling (DVFS)…

In this paper we report on the timing resolution of the first production of 50 micro-meter thick Ultra-Fast Silicon Detectors (UFSD) as obtained in a beam test with pions of 180 GeV/c momentum. UFSD are based on the Low-Gain Avalanche…

The use of precision timing measurements will be a major tool at the HL-LHC, where it will be used to suppress pile-up and to search for long-lived particles. To control a reference clock with sub-picosecond accuracy, we have fabricated in…

This article describes the design methodology to achieve reflective diode-based parametric frequency selective limiters (pFSLs) with low power thresholds ($P_{th}$) and sub-dB insertion-loss values ($IL^{s.s}$) for driving power levels…

We describe an FPGA-based, 96-channel, time-to-digital converter (TDC) intended for use with the Central Outer Tracker (COT) in the CDF Experiment at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each…