Related papers: TSPC-PFD: TSPC-Based Low-Power High-Resolution CMO…

Charge pump phase-locked loop with phase-frequency detector (CP-PLL) is an electrical circuit, widely used in digital systems for frequency synthesis and synchronization of the clock signals. In this paper a non-linear second-order model of…

High penetration of residential photovoltaic (PV) in low-voltage distribution networks (LVDN) makes the unbalance issue more sever due to the asymmetry of generation/load characteristic in different phases, and may lead to infeasible…

We present the design and test results of a Time-to-Digital-Converter (TDC). The TDC will be a part of the readout ASIC, called ETROC, to read out Low-Gain Avalanche Detectors (LGADs) for the CMS Endcap Timing Layer (ETL) of High-Luminosity…

A grid tied inverter converts DC voltage into AC voltage, while synchronizing it with the supply line phase and frequency. This paper presents an efficient, robust, and easy-to-implement grid tie mechanism. First, the grid tie mechanism was…

Non-contact scanning probe microscopy (SPM) has developed into a powerful technique to image many different properties of samples. The conventional method involves monitoring the amplitude, phase or frequency of a cantilever oscillating at…

An optical equivalent of the field-programmable gate array (FPGA) is of great interest to large-scale photonic integrated circuits. Previous programmable photonic devices relying on the weak, volatile thermo-optic or electro-optic effect…

Time-to-Digital Converters (TDCs) are a crucial tool in a wide array of fields, in particular for quantum communication, where time taggers performance can severely affect the quality of the entire application. Nowadays, FPGA-based TDCs…

A clock synchronizing circuit for repeaterless low swing interconnects is presented in this paper. The circuit uses a delay locked loop (DLL) to generate multiple phases of the clock, of which the one closest to the center of the eye is…

Synchronous reference frame phase-looked loop (SRF-PLL) techniques are widely used for interfacing and control applications in the power systems and energy conversion at large. Since a PLL system synchronizes its output with an exogenous…

Rapid single-flux quantum (RSFQ), a leading cryogenic superconductive electronics (SCE) technology, offers extremely low power dissipation and high speed. However, implementing RSFQ systems at VLSI complexity faces challenges, such as…

This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at 180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock frequency as compared to single edge triggered…

We present the design and performance characterization results of the novel Fermilab Constant Fraction Discriminator ASIC (FCFD) developed to readout low gain avalanche detector (LGAD) signals by directly using a constant fraction…

This work presents a new frequency acquisition method using semi-rotational frequency detection (SRFD) algorithm for a reference-less clock and data recovery (CDR) in a serial-link receiver. The proposed SRFD algorithm classifies the…

Power dissipation in integrated circuits is one of the major concerns to the research community, at the verge when more number of transistors are integrated on a single chip. The substantial source of power dissipation in sequential…

Microstrip three-way (that is, 4.8 dB) integrated filtering power divider (FPD) is presented in this paper. The proposed FPD evenly distributes an input power signal into three equal output signals. The design incorporates balanced signal…

Precise measurements of the frequency and phase of an electrical or optical signal play a key role in various branches of science and engineering. Tracking changing laser frequencies is especially demanding when the lasers themselves are…

In MIMO systems, the presence of phase noise is a significant factor that can degrade performance. For MIMO testbeds build from SDR devices, phase noise cannot be ignored, particular in applications that require phase synchronization. This…

This work discusses the suitability of typical power line communication (PLC) pulses for fault sensing in power lines via pulse-compression time-domain reflectometry (TDR). For this purpose, we first carefully outline a TDR system operating…

This paper presents a low hardware consumption, resolution-configurable, automatically calibrating Gray code oscillator time-to-digital converter (TDC) in Xilinx 16nm UltraScale+, 20nm UltraScale and 28nm Virtex-7 field-programmable gate…

The widespread deployment of phasor measurement unit (PMU) overpower systems makes it possible to monitor and analyze grid dynamics in real-time. Low-frequency oscillation is harmful to power system equipment and operation, and in the…