Related papers: Gate Electrostatic Controllability Enhancement in …

We investigate the effect of electrostatic gating on the thermoelectric power factor of p-type Si nanowires (NWs) of up to 20nm in diameter in the [100], [110] and [111] crystallographic transport orientations. We use atomistic…

A dual mode device behaving either as a field-effect transistor or a single electron transistor (SET) has been fabricated using silicon-on-insulator metal oxide semiconductor technology. Depending on the back gate polarisation, an electron…

We investigate the thermoelectric performance of 2D nanojunctions with gate tunable architectures and varying channel lengths from 3 to 12 nm using a combination of first principles simulations, including density functional theory, DFT with…

A vertical spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) is a promising low-power device for the post scaling era. Here, using a ferromagnetic-semiconductor GaMnAs-based vertical spin MOSFET with a GaAs channel layer,…

We present an analytical device model for a field-effect transistor based on a heterostructure which consists of an array of nanoribbons clad between the highly conducting substrate (the back gate) and the top gate controlling the…

The gate-voltage-induced suppression of critical currents in metallic superconductors observed recently [De Simoni et al., Nat. Nanotechnol. 13, 802 (2018)] has raised crucial questions regarding the nature and mechanism of the electric…

We present a simple and scalable technique for the fabrication of solution processed & local gated carbon nanotube field effect transistors (CNT-FETs). The approach is based on directed assembly of individual single wall carbon nanotube…

We report on the first realization of Nb-based \textit{all-metallic} gated Dayem nano-bridge field-effect transistors (Nb-FETs). These Josephson devices operate up to a temperature of $\sim 3$ K, and exhibit full suppression of the…

As silicon transistors scale toward future technology nodes, three-dimensional architectures -- including gate-all-around (GAA) nanoribbon and complementary field-effect transistors (CFETs) -- require channel widths in the tens of…

The observation of the gate-controlled supercurrent (GCS) effect in superconducting nanostructures increased the hopes for realizing a superconducting equivalent of semiconductor field-effect transistors. However, recent works attribute…

We investigated the effect of material choice and orientation in limiting source to drain tunneling (SDT) in nanowire (NW) p-MOSFETs. Si, Ge, GaSb, and Ge0.96Sn0.04 nanowire MOSFETs (NWFETs) were simulated using rigorous ballistic quantum…

We present a scaling theory of two-dimensional (2D) field effect transistors (FETs). For devices with channel thickness less than 4 nm, the device electrostatics is dominated by the physical gate oxide thickness and not the effective oxide…

Graphene field-effect transistors (GFETs) are among the most promising platforms for ultrasensitive chemical and biological sensing due to their high carrier mobility, large surface area, and low intrinsic noise. However, conventional…

Graphene is an attractive electrode material to contact nanostructures down to the molecular scale since it can be gated electrostatically. Gating can be used to control the doping and the energy level alignment in the nanojunction, thereby…

Fully depleted (FD) Silicon on Insulator (SOI) metal oxide Field Effect Transistor (MOSFET) Is the Leading Contender for Sun 65nm Regime. This paper presents a study of effects of work functions of metal gate on the performance of FD-SOI…

Stable, reproducible, scalable, addressable, and controllable hybrid superconductor-semiconductor (S-Sm) junctions and switches are key circuit elements and building blocks of gate-based quantum processors. The electrostatic field effect…

Integrating ferroelectric negative capacitance (NC) into the field-effect transistor (FET) promises to break fundamental limits of power dissipation known as Boltzmann tyranny. However, realizing the stable static negative capacitance in…

Sub-10nm wide graphene nanoribbon field-effect transistors (GNRFETs) are studied systematically. All sub-10nm GNRs afforded semiconducting FETs without exception, with Ion/Ioff ratio up to 10^6 and on-state current density as high as…

The first inversion-mode gate-all-around (GAA) III-V MOSFETs are experimentally demonstrated with a high mobility In0.53Ga0.47As channel and atomic-layer-deposited (ALD) Al2O3/WN gate stacks by a top-down approach. A well-controlled InGaAs…

Using a field-effect transistor (FET) configuration with solid Li-ion conductor (SIC) as gate dielectric, we have successfully tuned carrier density in FeSe$_{0.5}$Te$_{0.5}$ thin flakes, and the electronic phase diagram has been mapped…