Related papers: Negative Capacitance Enables FinFET Scaling Beyond…

This study simulated negative-capacitance double gate FinFETs with channel lengths ranging from 25nm to 100nm using TCAD. The results show that negative capacitance significantly reduces subthreshold swing as well as drain induced barrier…

In this paper, we take a fresh look at the physics and operation of Negative Capacitance FETs, and provide unambiguous feedback to the device designers by examining NC-FETs' design space for sub-60 mV/dec Subthreshold Swing (SS).…

In this paper, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of…

Using accurate Hybrid-Functional DFT coupled with the Non-Equilibrium Green's function (NEGF) formalism, we explore and benchmark the fundamental scaling limits of CNT-FETs against Si and 2D-material MoS$_2$ and HfS$_2$ Nanosheets,…

The main promise of tunnel FETs (TFETs) is to enable supply voltage ($V_{DD}$) scaling in conjunction with dimension scaling of transistors to reduce power consumption. However, reducing $V_{DD}$ and channel length ($L_{ch}$) typically…

This work presents a novel general compact model for 7nm technology node devices like FinFETs. As an extension of previous conventional compact model that based on some less accurate elements including one-dimensional Poisson equation for…

We report on measurements and modeling of FE HfZrO/SiO2 Ferroelectric-Dielectric (FE-DE) FETs which indicate that many of the phenomena attributed to Negative Capacitance can be explained by a delayed response of ferroelectric domain…

Steep-slope $\beta$-Ga$_2$O$_3$ nano-membrane negative capacitance field-effect transistors (NC-FETs) are demonstrated with ferroelectric hafnium zirconium oxide in gate dielectric stack. Subthreshold slope less than 60 mV/dec at room…

Boltzmann tyranny poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Negative…

While decreasing the oxide thickness in carbon nanotube field-effect transistors (CNFETs) improves the turn-on behavior, we demonstrate that this also requires scaling the range of the drain voltage. This scaling is needed to avoid an…

Negative capacitance (NC) in ferroelectrics, which stems from the imperfect screening of polarization, is considered a viable approach to lower voltage operation in the field-effect transistors (FETs) used in logic switches. In this paper,…

In this paper we propose a modified structure of TFET incorporating ferroelectric oxide as the complementary gate dielectric operating in negative capacitance zone, called the Negative Capacitance Tunnel FET (NCTFET). The proposed device…

In this paper, we study the vulnerability of 5nm node FinFET and nanowire (20nm gate length) and their corresponding SRAM under radiation. Ab initio tools, SRIM, PHITS, and GEANT4, are used to find the Linear Energy Transfer (LET) of…

It is well known that conventional Field Effect Transistors (FET's) require a change in the channel potential of at least 60 mV at 300K to effect a change in the current by a factor of ten, and this minimum subthreshold slope S puts a lower…

The study investigates the influence of negative capacitance on the transfer characteristics of vdW FETs on the heterophase of CIPS ferroelectric. Notably, a less pronounced NC resulting from the spatial distribution of the ferroelectric…

In this study, a SPICE model for negative capacitance vertical nanowire field-effect-transistor (NC VNW-FET) based on BSIM-CMG model and Landau-Khalatnikov (LK) equation was presented. Suffering from the limitation of short gate length…

Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10 nm scaling for high-performance CMOS applications. We show that a combination of…

Ion-Sensitive Field-Effect Transistors (ISFETs) form a wide-spread technology for sensing, thanks to their label-free detection and intrinsic CMOS compatibility. Their current sensitivity, {\Delta}ID/ID, for a given {\Delta}pH, however, is…

The observation of room temperature sub-60 mV/dec subthreshold slope (SS) in MOSFETs with ferroelectric (FE) layers in the gate stacks or in series with the gate has attracted much attention. Recently, we modeled this effect in the…

Digital In-memory computing improves energy efficiency and throughput of a data-intensive process, which incur memory thrashing and, resulting multiple same memory accesses in a von Neumann architecture. Digital in-memory computing involves…