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The upgrade of the ATLAS muon spectrometer for high-luminosity LHC requires new trigger and readout electronics for the various elements of the detector. We present the design of a time-to-digital converter (TDC) ASIC prototype for the…

This paper deals with the task of finding certified lower bounds for the performance of Analog to Digital Converters (ADCs). A general ADC is modeled as a causal, discrete-time dynamical system with outputs taking values in a finite set. We…

This article proposes a method for the measurement of Phase Noise (PN, or PM noise) and Amplitude Noise (AN, or AM noise) of Digital-to-Analog Converters (DAC) and Direct Digital Synthesizers (DDS) based on modulation-index amplification.…

Target parameter estimation in active sensing, and particularly radar signal processing, is a long-standing problem that has been studied extensively. In this paper, we propose a novel approach for target parameter estimation in cases where…

Two-channel modulo analog-to-digital converters (ADCs) enable high-dynamic-range signal sensing at the Nyquist rate per channel, but existing designs quantise both channel outputs independently, incurring redundant bitrate costs. This paper…

Low-resolution analog-to-digital converters (ADCs) in massive multi-user (MU) multiple-input multiple-output (MIMO) wireless systems can significantly reduce the power, cost, and interconnect data rates of infrastructure basestations. Thus,…

We propose a novel digital-to-analog converter (DAC) weighting architecture that statistically minimizes the distortion caused by random current mismatches. Unlike binary, thermometer-coded, and segmented DACs, the current weights of the…

This paper investigated the uplink of multi-user massive multi-input multi-output (MIMO) systems with a mixed analog-to-digital converter (ADC) receiver architecture, in which some antennas are equipped with costly full-resolution ADCs and…

A 28nm dense 6T-SRAM Digital(D)/Analog(A) Hybrid compute-in-memory (CIM) macro supporting complex num-ber MAC operation is presented. By introducing a 2D-weighted Capacitor Array, a hybrid configuration is adopted where digital CIM is…

In this work, we consider the acquisition of stationary signals using uniform analog-to-digital converters (ADCs), i.e., employing uniform sampling and scalar uniform quantization. We jointly optimize the pre-sampling and reconstruction…

The true-differential superconductor on-chip amplifier has complementary outputs that float with respect to chip ground. This improves signal integrity and compatibility with the receiving semiconductor stage. Both source-terminated and…

We present the prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for high-luminosity LHC operation. This ASIC is based on a previously submitted demonstrator ASIC designed for timing…

High hardware cost and high power consumption of massive multiple-input and multiple output (MIMO) are two challenges for the future wireless communications including beyond fifth generation (B5G) and sixth generation (6G). Adopting the…

In this paper, we provide an analytical framework for full-duplex (FD) massive multiple-input multiple-output (MIMO) cellular networks with low resolution analog-to-digital and digital-to-analog converters (ADCs and DACs). Matched filters…

Smarty is a fully-reconfigurable on-chip feed-forward artificial neural network (ANN) with ten integrated time-to-digital converters (TDCs) designed in a 16 nm FinFET CMOS technology node. The integration of TDCs together with an ANN aims…

We present the first ASIC implementation of jammer-resilient multi-antenna time synchronization. The ASIC implements a recent algorithm that mitigates jamming attacks on synchronization signals using multi-antenna processing. Our design…

In this paper, we propose and evaluate two novel double-sequence low-resolution frequency synchronization methods in millimeter-wave (mmWave) systems. In our system model, the base station uses analog beams to send the synchronization…

A crucial requirement for quantum computing, in particular for scalable quantum computing and error correction, is a fast and high-fidelity qubit readout. For semiconductor based qubits, one limiting factor for local low-power signal…

Deep learning hardware designs have been bottlenecked by conventional memories such as SRAM due to density, leakage and parallel computing challenges. Resistive devices can address the density and volatility issues, but have been limited by…

We present an analog silicon photomultiplier (SiPM) based on a standard 55 nm Bipolar-CMOS-DMOS (BCD) technology. The SiPM is composed of 16$\times$16 single-photon avalanche diodes (SPADs) and measures 0.29$\times$0.32 mm$^2$. Each SPAD…