Current-Steering DAC Architecture Design for Amplitude Mismatch Error Minimization
Signal Processing
2025-05-27 v1
Abstract
We propose a novel digital-to-analog converter (DAC) weighting architecture that statistically minimizes the distortion caused by random current mismatches. Unlike binary, thermometer-coded, and segmented DACs, the current weights of the proposed architecture are not an integer power of 2 or any other integer number. We present a heuristic algorithm for a static mapping of DAC input codewords into corresponding DAC switches. High-level Matlab simulations are performed to illustrate the static performance improvement over the segmented structure.
Cite
@article{arxiv.2505.18353,
title = {Current-Steering DAC Architecture Design for Amplitude Mismatch Error Minimization},
author = {Ramin Babaee and Shahab Oveis Gharan and Martin Bouchard},
journal= {arXiv preprint arXiv:2505.18353},
year = {2025}
}