Timing-Error Optimized Architecture for Current-Steering DACs
Signal Processing
2025-12-10 v1
Abstract
We propose a novel digital-to-analog converter (DAC) weighting architecture that statistically minimizes the distortion caused by random timing mismatches among current sources. To decode the DAC input codewords into corresponding DAC switches, we present three algorithms with varying computational complexities. We perform high-level Matlab simulations to illustrate the dynamic performance improvement over the segmented structure.
Cite
@article{arxiv.2512.08903,
title = {Timing-Error Optimized Architecture for Current-Steering DACs},
author = {Ramin Babaee and Shahab Oveis Gharan and Martin Bouchard},
journal= {arXiv preprint arXiv:2512.08903},
year = {2025}
}