Related papers: Cryogenic MOS Transistor Model
This paper presents a physics-based model for the threshold voltage in bulk MOSFETs valid from room down to cryogenic temperature (4.2 K). The proposed model is derived from Poisson's equation including bandgap widening, intrinsic…
Cryogenic characterization and modeling of 0.18um CMOS technology (1.8V and 5V) are presented in this paper. Several PMOS and NMOS transistors with different width to length ratios(W/L) were extensively characterized under various bias…
This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The…
Cryogenic CMOS technology (cryo-CMOS) offers a scalable solution for quantum device interface fabrication. Several previous works have studied the characterization of CMOS technology at cryogenic temperatures for various process nodes.…
Cryogenic semiconductor device models are essential in designing control systems for quantum devices and in benchmarking the benefits of cryogenic cooling for high-performance computing. In particular, the saturation of subthreshold swing…
Conventional CMOS technology operated at cryogenic conditions has recently attracted interest for its uses in low-noise electronics. We present one of the first characterizations of 180 nm CMOS technology at a temperature of 100 mK,…
On-chip thermometry at deep-cryogenic temperatures is vital in quantum computing applications to accurately quantify the effect of increased temperature on qubit performance. In this work, we present a sub-1 K temperature sensor in CMOS…
Cryogenic applications in high-energy physics (HEP) demand reliable, low-power CMOS electronics capable of operating at liquid nitrogen temperatures (77 K). The open-source SkyWater 130nm (SKY130) CMOS process has previously been shown to…
Power dissipation is a great challenge for the continuous scaling down and performance improvement of CMOS technology, due to thermionic current switching limit of conventional MOSFETs. In this work, we show that this problem can be…
This work presents a self-heating study of a 40-nm bulk-CMOS technology in the ambient temperature range from 300 K down to 4.2 K. A custom test chip was designed and fabricated for measuring both the temperature rise in the MOSFET channel…
A novel power-efficient analog buffer at liquid helium temperature is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation…
When designing and studying circuits operating at cryogenic temperatures understanding local heating within the circuits is critical due to the temperature dependence of transistor and noise behavior. We have investigated local heating…
Accurate on-chip temperature sensing is critical for the optimal performance of modern CMOS integrated circuits (ICs), to understand and monitor localized heating around the chip during operation. The development of quantum computers has…
Large power consumption of silicon CMOS electronics is a challenge in very-large-scale integrated circuits and a major roadblock to fault-tolerant quantum computation. Matching the power dissipation of Si-MOSFETs to the thermal budget at…
We report the design-technology co-optimization (DTCO) scheme to develop a 28-nm cryogenic CMOS (Cryo-CMOS) technology for high-performance computing (HPC). The precise adjustment of halo implants manages to compensate the threshold voltage…
Previous cryogenic electronics studies are most above 4.2K. In this paper we present the cryogenic characterization of a 0.18{\mu}m standard bulk CMOS technology(1.8V and 5V) at sub-kelvin temperature around 270mK. PMOS and NMOS devices…
Semiconductor integrated circuits operated at cryogenic temperature will play an essential role in quantum computing architectures. These can offer equivalent or superior performance to their room-temperature counterparts while enabling a…
This paper presents the design and benchmarking of cryogenic bulk-FETs using an experimentally calibrated TCAD framework that integrates 2-D electrostatics and interface-trap effects from $T = 2$ K to 300 K. For a 28-nm node device, carrier…
The extremely low threshold voltage (Vth) of native MOSFETs (Vth~0V@300K) is conducive to the design of cryogenic circuits. Previous research on cryogenic MOSFETs mainly focused on the standard threshold voltage (SVT) and low threshold…
We perform the characterization and modeling of a floating-gate device realized with a commercial 350-nm CMOS technology at cryogenic temperature. The programmability of the device offers a solution in the realization of a precise and…