Related papers: FPGA Online Tracking Algorithm for the PANDA Straw…
With present-day detectors in high energy physics one often faces fast analog pulses of a few nanoseconds length which cover large dynamic ranges. In many experiments both amplitude and timing information have to be measured with high…
In LHC Run 3, ALICE will increase the data taking rate significantly to 50 kHz continuous read-out of minimum bias Pb-Pb collisions. The reconstruction strategy of the online-offline computing upgrade foresees a first synchronous online…
In Monte Carlo radiation transport calculations, Woodcock-delta tracking is a common alternative to the more popular surface tracking technique. In this work we introduce a delta-tracking algorithm that tallies fluxes to a structured…
As the quantities of data recorded by embedded edge sensors grow, so too does the need for intelligent local processing. Such data often comes in the form of time-series signals, based on which real-time predictions can be made locally…
This paper describes a step by step approach for implementing a scalable and run-time adaptable multi-standard packet detector for orthogonal frequency divisional multiplexing (OFDM) based communication standards. The paper briefly…
Current and next-generation particle tracking detectors will incorporate precision timing capabilities with resolutions approaching tens of picoseconds. Using Technology Computer-Aided Design (TCAD) simulations of Low-Gain Avalanche Diode…
This document describes the technical layout and the expected performance of the Straw Tube Tracker (STT), the main tracking detector of the PANDA target spectrometer. The STT encloses a Micro-Vertex-Detector (MVD) for the inner tracking…
The Global Event Processor (GEP) FPGA is an area-constrained, performance-critical element of the Large Hadron Collider's (LHC) ATLAS experiment. It needs to very quickly determine which small fraction of detected events should be retained…
Region proposal is critical for object detection while it usually poses a bottleneck in improving the computation efficiency on traditional control-flow architectures. We have observed region proposal tasks are potentially suitable for…
This work introduces a highly efficient implementation of the transformer architecture on a Field-Programmable Gate Array (FPGA) by using the \texttt{hls4ml} tool. Given the demonstrated effectiveness of transformer models in addressing a…
Security issues are playing dominant role in today's high speed communication systems. A fast and compact FPGA based implementation of the Data Encryption Standard (DES) and Triple DES algorithm is presented in this paper that is widely…
The PANDA experiment will be built at the FAIR facility at Darmstadt (Germany) to perform accurate tests of the strong interaction through bar pp and bar pA annihilation's studies. To track charged particles, two systems consisting of a set…
In this work, we present the design and evaluation of a Processor Tracing System compliant with the RISC-V Efficient Trace specification for Instruction Branch Tracing. We integrate our system into the host domain of a state-of-the-art edge…
Hash table is a fundamental data structure for quick search and retrieval of data. It is a key component in complex graph analytics and AI/ML applications. State-of-the-art parallel hash table implementations either make some simplifying…
FPGA-based hardware accelerators are becoming increasingly popular due to their versatility, customizability, energy efficiency, constant latency, and scalability. FPGAs can be tailored to specific algorithms, enabling efficient hardware…
In this work, a serial on-line cluster reconstruction technique based on FPGA technology was developed to compress experiment data and reduce the dead time of data transmission and storage. At the same time, X-ray imaging experiment based…
We demonstrate an FPGA implementation of a parallel and reconfigurable architecture for sparse neural networks, capable of on-chip training and inference. The network connectivity uses pre-determined, structured sparsity to significantly…
Track reconstruction in high track multiplicity environments at current and future high rate particle physics experiments is a big challenge and very time consuming. The search for track seeds and the fitting of track candidates are usually…
FPGA is appropriate for fix-point neural networks computing due to high power efficiency and configurability. However, its design must be intensively refined to achieve high performance using limited hardware resources. We present an…
Real-time biosignal processing on wearable devices has attracted worldwide attention for its potential in healthcare applications. However, the requirement of low-area, low-power and high adaptability to different patients challenge…