Related papers: Can Tunnel Transistors Scale Below 10nm?
By means of numerical simulation, we study in this work the effects of uniaxial strain on transport properties of strained graphene heterojunctions and explore the possibility to achieve good performance of graphene transistors using these…
In the paper the version of the field effect tunnel nano transistor on quantum well is researched, where the control voltage is applied to the barriers surrounding the quantum well, and electron drain comes from the quantum well. Electrons…
2D material based tunnel FETs are among the most promising candidates for low power electronics applications since they offer ultimate gate control and high current drives that are achievable through small tunneling distances during the…
A vertical partial gate carbon nanotube (CNT) field-effect transistor (FET), which is amenable to the vertical CNT growth process and offers the potential for a parallel CNT array channel, is simulated using a self-consistent atomistic…
The sensitive conductance change of semiconductor nanowires and carbon nanotubes in response to binding of charged molecules provide a novel sensing modality which is generally denoted as nanoFET sensors. In this paper, we study the scaling…
The study of the effects of scaling on magnetic tunnel junction (MTJ) devices has become an important topic in the field of spin-based memory devices. Here, we investigate the effect of elastic dephasing on trilayer and pentalayer MTJ…
In this paper, we propose the application of a Dual Material Gate (DMG) in a Tunnel Field Effect Transistor (TFET) to simultaneously optimize the on-current, the off-current and the threshold voltage, and also improve the average…
This paper projects the enhanced drive current of a n-type electrostatically doped (ED) tunnel field-effect transistor (ED-TFET) based on heterojunction and band-gap engineering via TCAD 2-D device simulations. The homojunction ED-TFET…
In this work, the transport of tunnel field-effect transistor (TFET) based on vertically stacked hereto-structures from 2D transition metal dichalcogenide (TMD) materials is investigated by atomistic quantum transport simulations. WTe2-MoS2…
The scaling behaviors of graphene nanoribbon (GNR) Schottky barrier field-effect transistors (SBFETs) are studied by solving the non-equilibrium Green's function (NEGF) transport equation in an atomistic basis set self-consistently with a…
Amorphous semiconductors are important channel semiconductors in thin film transistors (TFTs) which serve not only active-matrix displays, but also flexible electronics for Internet of Things (IoT) applications. Nevertheless, a great…
Resonant frequencies of the two-dimensional plasma in FETs increase with the reduction of the channel dimensions and can reach the THz range for sub-micron gate lengths. Nonlinear properties of the electron plasma in the transistor channel…
The doped silicon regions (tubs) in PWFDSOI MOSFET cause significant reduction in OFF current by reducing the number of carriers contributing to the OFF current. The emphasis of the simulation and device physics study on PWFDSOI MOSFET…
With decreasing device dimensions, the performance of carbon nanotube field-effect transistors (CNFETs) is limited by high Off currents except at low drain voltages. We show that an asymmetric design improves the performance, reducing Off…
We investigate scaling of technologically relevant magnetic tunnel junction devices in the trilayer and pentalayer configurations by varying the cross-sectional area along the transverse direction using the non-equilibrium Green's function…
In recent part extensive simulation work has already been done on TFETs. However this is limited to device performance analysis. Evaluation of circuit performance is a topic that is very little touched. This is due to the non availability…
InAs/GaSb and similar materials systems have generated great interest as a heterojunction for tunnel field effect transistors (TFETs) due to favorable band alignment. However, little is currently understood about how such TFETs are affected…
An important consideration in miniaturizing transistors is maximizing the coupling between the gate and the semiconductor channel. A nanowire with a coaxial metal gate provides optimal gate-channel coupling, but has only been realized for…
Making ultra-short gate-length transistors significantly contributes to scaling the contacted gate pitch. This, in turn, plays a vital role in achieving smaller standard logic cells for enhanced logic density scaling. As we push the…
Vertical field effect transistors (VFETs) show many advantages such as high switching speed, low operating voltage, low power consumption, and miniaturization over lateral FETs. However, VFET still faces the main challenges of high…