Related papers: Can Tunnel Transistors Scale Below 10nm?

The influence of edge vacancies on the working ability of the planar graphene tunnel field-effect transistor (TFET) is studied at various concentrations and distributions (normal, uniform, periodic) of defects. All calculations are…

2D transition metal dichalcogenides (TMDs) have attracted a lot of attention recently for energy-efficient tunneling-field-effect transistor (TFET) applications due to their excellent gate control resulting from their atomically thin…

We present a compact model for Tunnel Field Effect Transistors (TFET), that captures sev- eral non-idealities such as the Trap Assisted Tunneling (TAT) originating from interface traps (Dit), along with Verilog-A implementation. We show…

Vertical tunneling field-effect-transistor (FET) based on graphene heterojunctions with layers of hBN is simulated by self-consistent quantum transport simulations. It is found that the asymmetric p-type and n-type conduction is due to work…

We study the channel width scaling of back-gated MoS2 metal-oxide-semiconductor field-effect transistors (MOSFETs) from 2 {\mu}m down to 60 nm. We reveal that the channel conductance scales linearly with channel width, indicating no evident…

Ultra-thin (UT) oxide semiconductors are promising candidates for back-end-of-line (BEOL) compatible transistors and monolithic three-dimensional integration. Experimentally, UT indium oxide (In$_2$O$_3$) field-effect transistors (FETs)…

Transistor miniaturization requires controlling gate leakage through ultrathin dielectrics and minimizing source/drain contact resistance. Although two-dimensional (2D) semiconductors offer excellent electrostatic control, their interfaces…

Using 2-D self-consistent ballistic quantum transport simulations, we investigate the short-channel behavior of graphene field-effect transistors and its impact on the device transconductance and subsequently the intrinsic cut-off frequency…

In the present work, we have investigated the performances of L shaped Vertical broken bandgapheterostructureInSb InAsn-channel tunnel field effect transistors TFETs of 4 nm thin channel structures with the gate lengths of 20nm. We have…

It is well known that conventional Field Effect Transistors (FET's) require a change in the channel potential of at least 60 mV at 300K to effect a change in the current by a factor of ten, and this minimum subthreshold slope S puts a lower…

A bilayer graphene based electrostatically doped tunnel field-effect transistor (BED-TFET) is proposed in this work. Unlike graphene nanoribbon TFETs in which the edge states deteriorate the OFF-state performance, BED-TFETs operate based on…

In this paper we have developed a two dimensional (2D) analytical model for surface potential and drain current for a long channel Dual Material Gate (DMG) Silicon-on-Insulator (SOI) Tunneling Field Effect Transistor (TFET). This model…

FinFET technology is prone to suffer from Line Edge Roughness (LER) based VT variation with scaling. To address this, we proposed an Epitaxially Defined (ED) FinFET (EDFinFET) as an alternate to FinFET architecture for 10 nm node and…

Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10 nm scaling for high-performance CMOS applications. We show that a combination of…

Tunnel field effect transistors (TFETs) utilizing semiconductor heterojunctions have shown promise for low energy logic but presently do not display subthreshold swings steeper than the room-temperature thermal limit of 60 mV/decade. These…

Nanoscale transistors require aggressive reduction of all channel dimensions: length, width, and thickness. While monolayer two-dimensional semiconductors (2DS) offer ultimate thickness scaling, good performance has largely been achieved…

High frequency operation of tunneling real-space transfer transistor (TRSTT) in the negative differential resistance (NDR) regime is assessed by calculating the device common source unity current gain frequency (fT) range with a small…

In this article, we investigate electrical transport properties in ultrathin body (UTB) MoS2 two-dimensional (2D) crystals with channel lengths ranging from 2 {\mu}m down to 50 nm. We compare the short channel behavior of sets of MOSFETs…

Using calibrated simulations, we report a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept. Without the need for any doping, the source and drain regions…

This study simulated negative-capacitance double gate FinFETs with channel lengths ranging from 25nm to 100nm using TCAD. The results show that negative capacitance significantly reduces subthreshold swing as well as drain induced barrier…