Related papers: Fabrication Process and Properties of Fully-Planar…
For high-performance superconducting quantum devices based on Josephson junctions (JJs) decreasing lateral sizes is of great importance. Fabrication of sub-\mu m JJs is challenging due to non-flat surfaces with step heights of up to several…
Increasing integration scale of superconductor electronics (SCE) requires employing kinetic inductors and self-shunted Josephson junctions (JJs) for miniaturizing inductors and JJs. We have been developing a ten-superconductor-layer…
To increase density of superconductor digital and neuromorphic circuits by 10x and reach integration scale of $10^8$ Josephson junctions (JJs) per chip, we developed a new fabrication process on 200-mm wafers, using self-shunted…
To increase integration scale of superconductor electronics, we are developing a new, SFQ7ee, node of the fabrication process at MIT Lincoln Laboratory. In comparison to the existing SFQ5ee node, we increased the number of fully planarized…
A minimal method to fabricate Al/AlO$_x$/Al Josephson junctions (JJs) using photolithography and argon etching, before metallization and oxidation, is demonstrated. JJs with areas ranging from 1 to 6 $\mu$m$^2$ can be fabricated and, with…
We have developed a novel fabrication process for ultra-small, full-epitaxial NbN Josephson junctions on a silicon (Si) substrate. A full-epitaxial NbN/AlN/NbN tri-layer was grown on a Si (100) wafer with a (200)-oriented TiN buffer layer.…
We investigated current-voltage characteristics of unshunted and externally shunted Josephson junctions (JJs) with high critical current densities, Jc, in order to extract their basic parameters and statistical characteristics for JJ…
We present our new fabrication Process for Superconductor Electronics (PSE2) that integrates two (2) layers of Josephson junctions in a fully planarized multilayer process on 200-mm wafers. The two junction layers can be, e.g., conventional…
Josephson junctions (JJs) are the key element of many devices operating at cryogenic temperatures. Development of time-efficient wafer-scale JJ characterization for process optimization and control of JJ fabrication is essential. Such…
We have developed a combined photolithography and electron-beam lithography fabrication process for sub-\mum to \mum-size Nb/Al-AlOx/Nb Josephson junctions. In order to define the junction size and protect its top electrode during anodic…
We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum…
Josephson junctions form the core circuit element in superconducting quantum computing circuits, single flux quantum digital logic circuits, and sensing devices such as SQUIDs. Aluminum oxide has typically been used as the tunnel barrier.…
Josephson tunnel junctions form the basis for various superconducting electronic devices. For this reason, enormous efforts are routinely taken to establish and later on maintain a scalable and reproducible wafer-scale manufacturing process…
The most commonly used physical realization of superconducting qubits for quantum circuits is a transmon. There are a number of superconducting quantum circuits applications, where Josephson junction critical current reproducibility over a…
We have developed a fabrication technology for the development of large-scale superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels uses four metal layers including 3 Nb…
We present a new process for fabricating vertical NbN-MgO-NbN Josephson junctions using self-aligned silicon nitride spacers. It allows for a wide range of junction areas from 0.02 um^2 to several 100 um^2. At the same time, it is suited…
A new fabrication process for superconducting integrated digital circuits is reported. We have developed the "SIMIT Nb04" fabrication technique for superconducting integrated circuits with Nb-based Josephson junctions based on the validated…
Josephson junction transistors and 50-junction arrays with linear junction dimensions from 200 nm down to 70 nm were fabricated from standard Nb/AlOx/Nb trilayers. The fabrication process includes electron beam lithography, dry etching,…
Currently, superconductor digital integrated circuits fabricated at HYPRES, Inc. can operate at clock frequencies of ~ 40 GHz. The circuits present multilayered structures containing tens of thousands of Nb/Al/AlOx/Nb Josephson junctions…
Reproducible High Tc Josephson junctions have been made in a rather simple two-step process using ion irradiation. A microbridge 1 to 5 micrometers wide is firstly designed by ion irradiating a c-axis-oriented YBa2Cu3O7 film through a gold…