Related papers: An efficient cntfet-based 7-input minority gate

Side-channel attacks have empowered bypassing of cryptographic components in circuits. Power side-channel (PSC) attacks have received particular traction, owing to their non-invasiveness and proven effectiveness. Aside from prior art…

The end of Moore's law for CMOS technology has prompted the search for low-power computing alternatives, resulting in several promising proposals based on magnetic logic[1-8]. One approach aims at tailoring arrays of nanomagnetic islands in…

Reversible logic has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its applications in low power CMOS design, cryptography, optical information processing and…

We have investigated the realizability of the controlled-NOT (CNOT) gate and characterized the gate operation by quantum process tomography for a chain of qubits, realized by electrons confined in self-assembled quantum dots embedded in the…

A simple scalable scheme is reported for fabricating suspended carbon nanotube field effect transistors (CNT-FETs) without exposing pristine as-grown carbon nanotubes to subsequent chemical processing. Versatility and ease of the technique…

Using accurate Hybrid-Functional DFT coupled with the Non-Equilibrium Green's function (NEGF) formalism, we explore and benchmark the fundamental scaling limits of CNT-FETs against Si and 2D-material MoS$_2$ and HfS$_2$ Nanosheets,…

The performance limits of the multilayer graphene nanoribbon (GNR) field-effect transistor (FET) are assessed and compared to those of monolayer GNR FET and carbon nanotube (CNT) FET. The results show that with a thin high-k gate insulator…

Recent experiments have demonstrated superconducting transmon qubits with semiconductor nanowire Josephson junctions. These hybrid gatemon qubits utilize field effect tunability characteristic for semiconductors to allow complete qubit…

Carbon nanotube field-effect transistors (FETs) with passivated coaxial gate structures have been fabricated after growth of contacted suspended single wall nanotubes (SWNTs) and subsequent coating with gate dielectrics. Electron…

Quantum mechanical effects induced by the miniaturization of complementary metal-oxide-semiconductor (CMOS) technology hamper the performance and scalability prospects of field-effect transistors. However, those quantum effects, such as…

We apply the method of compressed sensing (CS) quantum process tomography (QPT) to characterize quantum gates based on superconducting Xmon and phase qubits. Using experimental data for a two-qubit controlled-Z gate, we obtain an estimate…

We introduce a novel logic style with self-checking capability to enhance hardware reliability at logic level. The proposed logic cells have two-rail inputs/outputs, and the functionality for each rail of outputs enables construction of…

Crosstalk computing, involving engineered interference between nanoscale metal lines, offers a fresh perspective to scaling through co-existence with CMOS. Through capacitive manipulations and innovative circuit style, not only primitive…

Multi-Valued Logic (MVL) has more than one logic level defined to represent data whereas binary logic has 2 logic levels. It has been shown that the MVL circuits use the circuit resources more effectively at different voltage levels with…

We present a theoretical analysis of the selective darkening method for implementing quantum controlled-NOT (CNOT) gates. This method, which we recently proposed and demonstrated, consists of driving two transversely-coupled quantum bits…

A clever choice and design of gate sets can reduce the depth of a quantum circuit, and can improve the quality of the solution one obtains from a quantum algorithm. This is especially important for near-term quantum computers that suffer…

Several nanoelectronic devices have been already proved. However, no architecture which makes use of them provides a feasible opportunity to build medium/large systems. Nanoarchitecture proposals only solve a small part of the problems…

This work evaluates the performance of carbon nanotube field effect transistors (CNTFET) using few layer graphene as the contact electrode material. We present the experimental results obtained on the barrier height at CNT graphene junction…

Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10 nm scaling for high-performance CMOS applications. We show that a combination of…

Reconfigurable devices have garnered significant attention for alleviating the scaling requirements of conventional CMOS technology, as they require fewer components to construct circuits with similar function. Prior works required…