Related papers: An efficient cntfet-based 7-input minority gate
We have fabricated carbon nanotube (CN) field-effect transistors with multiple, individually addressable gate segments. The devices exhibit markedly different transistor characteristics when switched using gate segments controlling the…
A real-space quantum transport simulator for carbon nanoribbon (CNR) MOSFETs has been developed. Using this simulator, the performance of carbon nanoribbon (CNR) MOSFETs is examined in the ballistic limit. The impact of quantum effects on…
The continued evolution of CMOS technology demands materials and architectures that emphasize low power consumption, particularly for computations involving large scale data processing and multivariable optimization. Ferroelectric materials…
An evaluation of the gate capacitance of a field-effect transitor (FET) whose channel length and width are several ten nanometer, is a key point for sensors applications. However, experimental and precise evaluation of capacitance in the aF…
We report an experimental noise study of intermediate sized quasi ballistic semiconducting multiwalled carbon nanotube (IS-MWCNT) devices. The noise is two orders of magnitude lower than in singlewalled nanotubes (SWCNTs) and has no length…
We present quantum simulations of carbon nanotube field-effect transistors (CNT-FETs) based on top-gated architectures and compare to electrical characterization on devices with 15 nm channel lengths. A non-equilibrium Green's function…
This paper reviews the current status of graphene transistors as potential supplement to silicon CMOS technology. A short overview of graphene manufacturing and metrology methods is followed by an introduction of macroscopic graphene field…
Truly polymorphic circuits, whose functionality/circuit behavior can be altered using a control variable, can provide tremendous benefits in multi-functional system design and resource sharing. For secure and fault tolerant hardware designs…
In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272$\mu$W in 0.35$\mu$m technology with supply voltage of 3.3V. Minimum level for high output of 2.05V and maximum level for…
Carbon Nanotube (CNT) is one of the most significant materials for the development of faster and improved performance of nano-scaled transistors. This paper aims at analyzing a trade-off between device performance and device size of CNT…
Carbon nanotubes with their outstanding electrical and mechanical properties are suggested as interconnect material of the future and as switching devices, which could outperform silicon devices. In this paper we will introduce nanotubes,…
The advanced nanoscale integration available in silicon complementary metal-oxide-semiconductor (CMOS) technology provides a key motivation for its use in spin-based quantum computing applications. Initial demonstrations of quantum dot…
In nanoelectronic circuit synthesis, the majority gate and the inverter form the basic combinational logic primitives. This paper deduces the mathematical formulae to estimate the logical masking capability of majority gates, which are used…
Compute-in-memory (CiM) is a promising approach to alleviating the memory wall problem for domain-specific applications. Compared to current-domain CiM solutions, charge-domain CiM shows the opportunity for higher energy efficiency and…
This work presents a novel general compact model for 7nm technology node devices like FinFETs. As an extension of previous conventional compact model that based on some less accurate elements including one-dimensional Poisson equation for…
While quantum computing holds great potential in combinatorial optimization, electronic structure calculation, and number theory, the current era of quantum computing is limited by noisy hardware. Many quantum compilation approaches can…
Gate capacitances of back-gated nanowire field-effect transistors (NW-FETs) are calculated by means of finite element methods and the results are compared with analytical results of the ``metallic cylinder on an infinite metal plate…
This paper presents OptGM, an optimized gate merging method designed to mitigate negative bias temperature instability (NBTI) in digital circuits. First, the proposed approach effectively identifies NBTI-critical internal nodes, defined as…
We investigate the feasibility of combining Raman optical lattices with a quantum computing architecture based on lattice-confined magnetically interacting neutral atoms. A particular advantage of the standing Raman field lattices comes…
We introduce a hybrid qubit based on a semiconductor nanowire with an epitaxially grown superconductor layer. Josephson energy of the transmon-like device ("gatemon") is controlled by an electrostatic gate that depletes carriers in a…