Related papers: III-V Gate-all-around Nanowire MOSFET Process Tech…
Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10 nm scaling for high-performance CMOS applications. We show that a combination of…
GaAs-based nanowires are among the most promising candidates for realizing a monolithical integration of III-V optoelectronics on the Si platform. To realize their full potential for applications as light absorbers and emitters, it is…
3D NAND enables continuous NAND density and cost scaling beyond conventional 2D NAND. However, its poly-Si channel suffers from low mobility, large device variations, and instability caused by grain boundaries. Here, we overcome these…
Two-dimensional (2D) materials, such as molybdenum disulfide (MoS2), have been shown to exhibit excellent electrical and optical properties. The semiconducting nature of MoS2 allows it to overcome the shortcomings of zero-bandgap graphene,…
We propose a semi-suspended device structure and construct nanogapped, hysteresis-free field-effect transistors (FETs), based on the van der Waals stacking technique. The structure, which features a semi-suspended channel above a…
In this study, InSb nanowires have been formed by electrodeposition and integrated into NW-FETs. NWs were formed in porous anodic alumina (PAA) templates, with the PAA pore diameter of approximately 100 nm defining the NW diameter.…
We demonstrate an exotic doubled-channeled NT GAAFET (DC NT GAAFET) structure with Ion boost in comparison with NT GAAFET and NW GAAFET with the same footprint. Ion gains of 64.8% and 1.7 times have been obtained in DC NT GAAFET in compared…
The AlGaAs material platform has been intensively used to develop nonlinear photonic devices on-a-chip, thanks to its superior nonlinear optical properties. We propose a new AlGaAs waveguide geometry, called half-core etched, which…
Parallel and monolithic 3D integration directions offer pathways to realize 3D integrated circuits (ICs) but still lead to layer-by-layer implementations, each functional layer being composed in 2D first. This mindset causes challenging…
Steep-slope $\beta$-Ga$_2$O$_3$ nano-membrane negative capacitance field-effect transistors (NC-FETs) are demonstrated with ferroelectric hafnium zirconium oxide in gate dielectric stack. Subthreshold slope less than 60 mV/dec at room…
As metal-oxide-semiconductor field-effect transistors (MOSFET) channel lengths (Lg) are scaled to lengths shorter than Lg<8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario a heavier transport…
In-plane semiconductor nanowires with complex branched geometries, prepared via selective area growth (SAG), offer a versatile platform for advanced electronics, optoelectronics, and quantum devices. However, defects and disorder at the…
Core-shell germanium nanowire (GeNW) is formed with a single-crystalline Ge core and concentric shells of nitride and silicon passivation layer by chemical vapor deposition (CVD), an Al2O3 gate dielectric layer by atomic layer deposition…
Embedding quantum dots (QDs) on nanowire (NW) sidewalls allows the integration of multi-layers of QDs into the active region of radial p-i-n junctions to greatly enhance light emission/absorption. However, the surface curvature makes the…
Field-plated (FP) depletion-mode MOVPE-grown $\beta$-Ga$_2$O$_3$ lateral MESFETs are realized with superior reverse breakdown voltages and ON currents. A sandwiched SiN$_x$ dielectric field plate design was utilized that prevents…
A vertical partial gate carbon nanotube (CNT) field-effect transistor (FET), which is amenable to the vertical CNT growth process and offers the potential for a parallel CNT array channel, is simulated using a self-consistent atomistic…
In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We…
We report here the first realization of top-down silicon nanowires (SiNW) transduced by both junction-less field effect transistor (FET) and the piezoresistive (PZR) effect. The suspended SiNWs are among the smallest top-down SiNWs reported…
Junctionless Nanowire Field-Effect Transistors (JNFETs), where the channel region is uniformly doped without the need for source-channel and drain-channel junctions or lateral doping abruptness, are considered an attractive alternative to…
Low-dimensional materials such as layered semiconductors or carbon nanotubes (CNTs) have been attracting increasing attention in the last decades due to their inherent scaling properties, which become fundamental to sustain the scaling in…