Related papers: Extended-p+ Stepped Gate (ESG) LDMOS for Improved …
We propose a novel Forked-Contacts, Dynamically-Doped Multigate transistor as ultimate scaling booster for both Si and 2D materials in aggressively-scaled nanosheet devices. Using accurate dissipative DFT-NEGF atomistic-simulation…
In this work, the source structure of an n-type thin-film tunneling FET is engineered to get better performance. An ultra-thin SiGe along with Si is used in the source of silicon-based TFET. Two structures are compared with conventional…
We show that a periodic multi-grated-gate structure can be applied to THz plasmonic FETs (TeraFETs) to improve the THz detection sensitivity. The introduction of spatial non-uniformity by separated gate sections creates regions with…
Improving the efficiency of edge detection in embedded applications, such as UAV control, is critical for reducing system cost and power dissipation. Field programmable gate arrays (FPGA) are a good platform for making improvements because…
A new Schottky-gate Bipolar Mode Field Effect Transistor (SBMFET) is proposed and verified by two-dimensional simulation. Unlike in the case of conventional BMFET, which uses deep diffused p+-regions as the gate, the proposed device uses…
In this paper, we present the unique features exhibited by modified asymmetrical Double Gate (DG) silicon on insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the…
Graph transformers achieve strong results on molecular and long-range reasoning tasks, yet remain hampered by over-smoothing (the progressive collapse of node representations with depth) and attention entropy degeneration. We observe that…
Design considerations for a below 100 nm channel length SOI MOSFET with electrically induced shallow source/drain junctions are presented. Our simulation results demonstrate that the application of induced source/drain extensions to the SOI…
We present a study of the performance of the trapped-ion driven geometric phase gates introduced in [New J. Phys. 15, 083001 (2013)] when realized in a stimulated Raman transition. We show that the gate can achieve errors below the…
Phase change memories (PCM) is an emerging type of non-volatile memory that has shown a strong presence in the data-storage market. This technology has recently attracted significant research interest in the development of non-Von Neumann…
Long Short-term Memory Networks (LSTMs) are a vital Deep Learning technique suitable for performing on-device time series analysis on local sensor data streams of embedded devices. In this paper, we propose a new hardware accelerator design…
RF-induced micromotion in trapped ion systems is typically minimised or circumvented to avoid off-resonant couplings for adiabatic processes such as multi-ion gate operations. Non-adiabatic entangling gates (so-called `fast gates') do not…
Recent advancements in 3D Gaussian Splatting (3DGS) have shifted the focus toward balancing reconstruction fidelity with computational efficiency. In this work, we propose ImprovedGS+, a high-performance, low-level reinvention of the…
The needle bio-potential sensors for measuring muscle and brain activity need invasive surgical targeted muscle reinnervation (TMR) and a demanding process to maintain, but surface bio-potential sensors lack clear bio-signal reading…
The aim of this work is to present the optimization of the gate trench module for use in vertical GaN devices in terms of cleaning process of the etched surface of the gate trench, thickness of gate dielectric and magnesium concentration of…
In the standard MOSFET description of the drain current $I_{D}$ as a function of applied gate voltage $V_{GS}$, the subthreshold swing $SS(T)\equiv dV_{GS}/d\log I_{D}$ has a fundamental lower limit as a function of temperature $T$ given by…
Edge deployment of transformer-based models increasingly relies on ASIC accelerators due to their high performance and energy efficiency, achieved through optimized dataflows, specialized architectures, low-bitwidth computation, and…
This paper studies a ground-segment implementation problem in 5G non-terrestrial networks (NTN): once UE-side geometric pre-compensation has produced a coarse timing/frequency prior, can an edge-side residual loop keep the uplink inside an…
In this letter we discuss how the short channel behavior in sub 100 nm channel range can be improved by inducing a step surface potential profile at the back gate of an asymmetrical double gate (DG) Silicon-On-Insulator (SOI)…
This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed…