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Agentic Test-Time Scaling (TTS) has delivered state-of-the-art (SOTA) performance on complex software engineering tasks such as code generation and bug fixing. However, its practical adoption remains limited due to significant computational…
Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC…
This letter reports high-performance $\mathrm{\beta} Ga2O3 thin channel MOSFETs with T-gate and degenerately doped source/drain contacts regrown by MOCVD. Gate length scaling (LG= 160-200 nm) leads to a peak drain current (ID,MAX) of 285…
The impact semiconductor drift step recovery diodes (DSRDs) can have on high-power microwave applications make them a device of interest for future solid-state electronics. However, there is little known about their functionality and…
We present a gate-voltage tunable transmon qubit (gatemon) based on planar InAs nanowires that are selectively grown on a high resistivity silicon substrate using III-V buffer layers. We show that low loss superconducting resonators with an…
Electrochemical energy storage (ES) units (e.g. batteries) have been field-validated as an efficient back-up resource that enhance resilience of the distribution system in case of natural disasters. However, using these units for resilience…
Electrodynamic Dust Shield (EDS) technology is a dust mitigation strategy that is commonly studied for applications such as photovoltaics or thermal radiators where soiling of the surfaces can reduce performance. The goal of the current…
To reduce the leakage power of inactive (dark) silicon components, modern processor systems shut-off these components' power supply using low-leakage transistors, called power-gates. Unfortunately, power-gates increase the system's…
The matrix-free gather-batched-GEMM-scatter pattern eliminates global stiffness assembly for three-dimensional SIMP topology optimization, but the conventional three-stage implementation forces avoidable DRAM traffic between stages. We…
A MOSFET threshold voltage extraction method covering the entire range of drain-to-source voltage, from linear to saturation modes, is presented. Transconductance-to-current ratio is obtained from MOSFET transfer characteristics measured at…
We demonstrate a simple and scalable approach to increase conversion efficiencies of nonlinear metasurfaces by incorporating them into multipass cells and by letting the pump beam to interact with the metasurfaces multiple times. We…
As capacity and complexity of on-chip cache memory hierarchy increases, the service cost to the critical loads from Last Level Cache (LLC), which are frequently repeated, has become a major concern. The processor may stall for a…
With 3D-stacked DRAM architectures becoming more prevalent, it has become important to find ways to characterize and mitigate the adverse effects that can hinder their inherent access parallelism and throughput. One example of such…
Tunneling field-effect transistors (TFETs) have gained a great deal of recent interest due to their potential to reduce power dissipation in integrated circuits. One major challenge for TFETs so far has been achieving high drive currents,…
Small-diameter Drift Tube (sMDT) detectors with 15 mm tube diameter have proven to be excellent candidates for precision muon tracking detectors in experiments at future hadron colliders like HL-LHC and FCC-hh where unprecedentedly high…
We report on the demonstration of a deep sub-micron normally-off AlGaN/GaN HEMT with high on-current and high threshold voltage (VTH). The high-performance device was realized by utilizing a gate recess with length and depth of 200 nm and…
Edge Gaussian splatting (EGS), which aggregates data from distributed clients (e.g., drones) and trains a global GS model at the edge (e.g., ground server), is an emerging paradigm for scene reconstruction in low-altitude economy. Unlike…
Many modern embedded systems have end-to-end (EtoE) latency constraints that necessitate precise timing to ensure high reliability and functional correctness. The combination of High-Level Synthesis (HLS) and Design Space Exploration (DSE)…
Frequency-domain multiplexing is a readout technique for transition edge sensor bolometer arrays used on modern CMB experiments, including the SPT-3G receiver. Here, we present design details and performance measurements for a low-parasitic…
Spins in semiconductor quantum dots hold great promise as building blocks of quantum processors. Trapping them in SiMOS transistor-like devices eases future industrial scale fabrication. Among the potentially scalable readout solutions,…