Related papers: Variable Threshold MOSFET Approach (Through Dynami…
We propose a novel hybrid single-electron device for reprogrammable low-power logic operations, the magnetic single-electron transistor (MSET). The device consists of an aluminium single-electron transistors with a GaMnAs magnetic…
The CMOS integrated chips at advanced technology nodes are becoming more vulnerable to various sources of faults like manufacturing imprecisions, variations, aging, etc. Additionally, the intentional fault attacks (e.g., high power…
Most chip designers outsource the manufacturing of their integrated circuits (ICs) to external foundries due to the exorbitant cost and complexity of the process. This involvement of untrustworthy, external entities opens the door to major…
The goal of this work is to minimize the energy dissipation of embedded controllers without jeopardizing the quality of control (QoC). Taking advantage of the dynamic voltage scaling (DVS) technology, this paper develops a performance-aware…
Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10 nm scaling for high-performance CMOS applications. We show that a combination of…
Real-time detection of moving objects involves memorisation of features in the template image and their comparison with those in the test image. At high sampling rates, such techniques face the problems of high algorithmic complexity and…
The trench gate MOSFET has established itself as the most suitable power device for low to medium power applications by offering the lowest possible ON resistance among all MOS devices. The evolution of the trench gate power MOSFET has been…
To reduce the leakage power of inactive (dark) silicon components, modern processor systems shut-off these components' power supply using low-leakage transistors, called power-gates. Unfortunately, power-gates increase the system's…
In most digital-to-time converter (DTC) based applications, apart from maintaining low integral non-linearity (INL), it is also required of the system to achieve a wide frequency translation range. To achieve this performance, we present a…
In this paper we propose a modified structure of TFET incorporating ferroelectric oxide as the complementary gate dielectric operating in negative capacitance zone, called the Negative Capacitance Tunnel FET (NCTFET). The proposed device…
Randomization of the trap state of defects present at the gate Si-SiO$_2$ interface of MOSFET is responsible for the low-frequency noise phenomena such as Random Telegraph Signal (RTS), burst, and 1/\textit{f} noise. In a previous work,…
Vertical field effect transistors (VFETs) show many advantages such as high switching speed, low operating voltage, low power consumption, and miniaturization over lateral FETs. However, VFET still faces the main challenges of high…
This paper presents a novel dissipativity-based distributed droop-free control approach for the voltage regulation problem in DC microgrids (MGs) comprised of an interconnected set of distributed generators (DGs), loads, and power lines.…
We report the design-technology co-optimization (DTCO) scheme to develop a 28-nm cryogenic CMOS (Cryo-CMOS) technology for high-performance computing (HPC). The precise adjustment of halo implants manages to compensate the threshold voltage…
With the increasing digital services demand, performance and power-efficiency become vital requirements for digital circuits and systems. However, the enabling CMOS technology scaling has been facing significant challenges of device…
Tunnel field effect transistor (TFET) devices are attractive as they show good scalability and have very low leakage current. However they suffer from low on-current and high threshold voltage. In order to employ the TFET for circuit…
The mobility of emerging (e.g., two-dimensional, oxide, organic) semiconductors is commonly estimated from transistor current-voltage measurements. However, such devices often experience contact gating, i.e., electric fields from the gate…
This paper presents OptGM, an optimized gate merging method designed to mitigate negative bias temperature instability (NBTI) in digital circuits. First, the proposed approach effectively identifies NBTI-critical internal nodes, defined as…
Phase change materials (PCMs) play a pivotal role in the development of advanced thermal devices due to their reversible phase transitions, which drastically modify their thermal and optical properties. In this study, we present an…
Silicon-based quantum computing has the potential advantages of low cost, high integration density, and compatibility with CMOS technologies. The detuning mechanism has been used to experimentally achieve silicon two-qubit quantum gates and…