Related papers: Use of negative capacitance to provide a sub-thres…
The charge doped into a semiconductor in a field effect transistor (FET) is generally confined to the interface of the semiconductor. A planar step at the interface causes a potential drop due to the strong electric field of the FET, which…
The use of SrTiO$_3$ dielectrics as high-permittivity insulator in organic thin film field effect transistors (FET) is evaluated. Field-effect transistors with sputtered SrTiO$_3$ and copper-phthalocyanine (CuPc) as semiconducting layer…
In a ferromagnet/superconductor/ferromagnet (F/S/F) superconducting spin-valve (SSV), a change of the magnetization alignment of the two F layers modulates the critical temperature (Tc) of the S layer. The Tc-switching (the SSV effect) is…
Using field-effect transistors (FETs) to explore atomically thin magnetic semiconductors with transport measurements is difficult, because the very narrow bands of most 2D magnetic semiconductors cause carrier localization, preventing…
We study the surface conductivity of a field-effect transistor (FET) made of periodic array of spherical semiconductor nanocrystals (NCs). We show that electrons introduced to NCs by the gate voltage occupy one or two layers of the array.…
Integrated circuits (ICs) that can operate at high temperature have a wide variety of applications in the fields of automotive, aerospace, space exploration, and deep-well drilling. Conventional silicon-based complementary…
Power dissipation has become a major obstacle in performance scaling of modern integrated circuits, and has spurred the search for devices operating at lower voltage swing. In this letter, we study p-i-n band-to-band tunneling field effect…
We report negative capacitance at low frequencies in organic semiconductor based diodes and show that it appears only under bipolar injection conditions. We account quantitatively for this phenomenon by the recombination current due to…
Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire…
For high-electron-mobility transistors based on two-dimensional electron gas (2DEG) within a quantum well, such as those based on AlGaN/GaN heterostructure, a Schottky-gate is used to maximize the amount of charge that can be induced and…
In a continuous search for the energy-efficient electronic switches, a great attention is focused on tunnel field-effect transistors (TFETs) demonstrating an abrupt dependence of the source-drain current on the gate voltage. Among all…
Recent experiments have shown the possibility of tuning the transport properties of metallic nanosized superconductors through a gate voltage. These results renewed the longstanding debate on the interaction between electrostatic fields and…
A novel room temperature capacitance-to-phase transducer is described, which uses a modified All-Pass filter architecture combined with a simple series resonant tank circuit with a moderate Q-factor. It is fashioned from a discrete inductor…
The dielectric engineered tunnel field-effect transistor (DE-TFET) as a high performance steep transistor is proposed. In this device, a combination of high-k and low-k dielectrics results in a high electric field at the tunnel junction. As…
We report a strategy to design nanoscale cold-source field-effect transistors (CS-FETs) with bias-independent sub-60 mV/dec subthreshold swing (SS). By first-principles calculations and quantum-transport simulations, we reveal that the…
We present a current and charge conserving theory for the low frequency admittance of a quantum point contact. We derive expressions for the electrochemical capacitance and the displacement current. The latter is determined by the {\em…
Graphene field effect transistors commonly comprise graphene flakes lying on SiO2 surfaces. The gate-voltage dependent conductance shows hysteresis depending on the gate sweeping rate/range. It is shown here that the transistors exhibit two…
Conventional readout of a superconducting nanowire single-photon detector (SNSPD) sets an upper bound on the output voltage to be the product of the bias current and the load impedance, $I_\mathrm{B}\times Z_\mathrm{load}$, where…
This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at 180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock frequency as compared to single edge triggered…
The high current density required by Magnetic Tunneling Junction (MTJ) switching driven by Spin Transfer Torque (STT) effect leads to large power consumption and severe reliability issues therefore hinder the timetable for STT Magnetic…