A status report is given of the QCDOC project, a massively parallel computer optimized for lattice QCD using system-on-a-chip technology. We describe several of the hardware and software features unique to the QCDOC architecture and present performance figures obtained from simulating the current VHDL design of the QCDOC chip with single-cycle accuracy.
@article{arxiv.hep-lat/0110124,
title = {Status of the QCDOC project},
author = {P. A. Boyle and D. Chen and N. H. Christ and C. Cristian and Z. Dong and A. Gara and B. Joó and C. Kim and L. Levkova and X. Liao and G. Liu and R. D. Mawhinney and S. Ohta and T. Wettig and A. Yamaguchi},
journal= {arXiv preprint arXiv:hep-lat/0110124},
year = {2010}
}