QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation.
@article{arxiv.hep-lat/0309096,
title = {Hardware and software status of QCDOC},
author = {P. A. Boyle and D. Chen and N. H. Christ and M. Clark and S. D. Cohen and C. Cristian and Z. Dong and A. Gara and B. Joo and C. Jung and C. Kim and L. Levkova and X. Liao and G. Liu and R. D. Mawhinney and S. Ohta and K. Petrov and T. Wettig and A. Yamaguchi},
journal= {arXiv preprint arXiv:hep-lat/0309096},
year = {2010}
}