The architecture of a new class of computers, optimized for lattice QCD calculations, is described. An individual node is based on a single integrated circuit containing a PowerPC 32-bit integer processor with a 1 Gflops 64-bit IEEE floating point unit, 4 Mbyte of memory, 8 Gbit/sec nearest-neighbor communications and additional control and diagnostic circuitry. The machine's name, QCDOC, derives from ``QCD On a Chip''.
Cite
@article{arxiv.hep-lat/0011004,
title = {QCDOC: A 10-teraflops scale computer for lattice QCD},
author = {D. Chen and N. H. Christ and C. Cristian and Z. Dong and A. Gara and K. Garg and B. Joo and C. Kim and L. Levkova and X. Liao and R. D. Mawhinney and S. Ohta and T. Wettig},
journal= {arXiv preprint arXiv:hep-lat/0011004},
year = {2010}
}